XTNETA1622DW datasheet(24/68 Pages) TI1

24 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

segmentation data structures

The transmit operation uses data structures that reside in both control memory, host memory, and internal

registers. Control memory is used to store dynamic parameters associated with the segmentation of a particular

packet, as well as configuration information for each individual transmit group that is initialized by the host at

startup. Control memory contains both dynamic and static parameters. Host memory contains the data buffers

that are to be segmented and the information required to begin segmentation of an individual data buffer into

ATM cells. The information contained in host memory is specific to the data buffers currently being transmitted

and is constantly being updated.

The transmit data structures that reside in host memory are the data buffers, which include the interrupt and

the associated descriptor information, and the transmit completion rings with/without packet-segmentation

rings. The transmit completion rings contain the addresses of the data buffers that have completed

segmentation and are used by the host to reclaim buffers. The host must decide at initialization whether a

transmit DMA channel uses the transmit completion ring with or without interrupt. The difference between the

two rings is that when an entry is posted to the completion ring with interrupt, an interrupt is generated by the

TNETA1570. When an entry is posted to the completion ring without interrupt, an interrupt is not generated. The

size of the transmit completion rings is variable and is set by the host at initialization by writing to the

transmit-completion-ring-size register located inside the TNETA1570.

The packet-segmentation rings are used to queue up packets for transmission. The location of the first buffer

in a packet that is to be transmitted is written into the segmentation-ring entry. Each packet-segmentation ring

has up to 256 entries. Since there is a separate packet-segmentation ring for each transmit DMA channel, there

is a maximum of 1023 segmentation rings in host memory.

The transmit data structures that reside in control memory are the scheduler table and the transmit DMA state

table. The scheduler table is used to schedule the different virtual connections and contains 3100 32-bit words

with two 16-bit entries per word. This provides a resolution of approximately 32 Kbit/s. The transmit DMA state

table contains the DMA-channel-state information. It has a maximum of 1023 entries.

Internal registers are used for the scheduler-table size, TX packet-segmentation-ring size, TX completion-ring

pointers, and the TX completion-ring size.

HOST MEMORY

Data buffers with descriptor entry

TX completion ring with interrupt

TX completion ring without interrupt

Packet-segmentation rings

CONTROL MEMORY

Scheduler table

TX DMA state table

reassembly data structures

The receive operation, as the transmit, uses data structures in both host memory and control memory to

reassemble incoming packets. The actual reassembly of a packet occurs in host memory; the device contains

only enough internal buffering to absorb the effects of bus transactions and availability. Control memory is used

to maintain the status and configuration information necessary to complete the reassembly of a packet.

The receive data structures that reside in host memory are the data buffers (including the descriptor

information), receive completion-rings with/without interrupt, and receive free-buffer rings (FIFOs). A receive

completion-ring entry contains the address of the first data buffer of a packet that has completed reassembly

and is used to notify the host that a packet has been received. The host must decide at initialization whether

XTNETA1622DW 数据表(PDF) 24 Page - Texas Instruments

XTNETA1622DW 数据表(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载