TNETX4080GGP datasheet(2/64 Pages) TI1

2 / 64 page

TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

Switching Engine

(Queue Manager)

Rambus

DRAM

Controller

VLAN 802.1Q

and

Address-Lookup Engine

1024 CAM

Hardware

RMON

and

Etherstat

MIB

JTAG

I/F

LED

I/F

MDIO

I/F

100-M

Management

MAC

CPU I/F

With

DMA

EEPROM

I/F

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

10/100

MAC

MII

Local Packet Switching Memory

Figure 1. TNETX4080 Block Diagram

The TNETX4080 memory solution combines low cost and extremely high bandwidth, using 600-Mbit/pin/s

concurrent RDRAM. The packet memory has been implemented to maximize efficiency with the RDRAM

architecture. Data is buffered internally and transferred to/from packet memory in 128-byte bursts. Extremely

high memory bandwidth is maintained, allowing all ports to be active without bottlenecking at the memory buffer.

The TNETX4080 is fabricated with a 2.5-V technology. The inputs are 3.3-V tolerant and the outputs are capable

of directly interfacing to TTL levels. This provides the customer with a broad choice of interfacing device options.

Signal names and their terminal assignments are sorted alphabetically in Table 1.

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