TNETX4080GGP datasheet(34/64 Pages) TI1

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TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 10. LED Status Bit Definitions and Shift Order

ORDER

NAME

FUNCTION

slast = 0

slast = 1

NAME

FUNCTION

1st–12th

11th–22nd

SW0–SW11

Software LEDs 0–11. These allow additional software-controlled status to be displayed. These

12 LEDs reflect the values of bits 0–11 of the swied field in LEDControl at the moment that the LED

interface samples them. If this occurs between writes to the most significant and least significant

bytes of LEDControl, these values appear on the LEDs, separated by 1/16th of a second.

13th–21st

1st–9th

P00–P08

Port status LEDs 0–8. These nine LEDs indicate the status of ports 0–8, in this order (port 0 is output

first). Note that port 9 (management port) does not have an LED. The transmit multicast content

of these bits can be controlled by the txais bit in LEDControl. Note that IEEE Std 802.3x pause

frames never appear on the LEDs as port activity. The port’s LED toggles each 1/16th of a second

if there was any frame traffic (other than pause frames) on the port during the previous 1/16th of

a second.

22nd

10th

C08

Port 8 collision LED. LED is extinguished if the port 8 is not in PMA mode. It indicates the collisions

on port 8 and toggles each 1/16th of a second if there is a collision on the port during the previous

1/16th of a second.

23rd

FLOW

Flow control. LED is on when the internal flow control is enabled and active. Active means that flow

control was asserted during the previous 1/16th of a second.

24th

FAULT

Fault. LED indicates:

– the EEPROM CRC was invalid.

– an external DRAM parity error has occurred.

– the FITLED in LEDControl has been set. The CRC and parity error indications are cleared

by hardware reset (pin or DIO). The CRC error indication also is cleared by setting load to

1. The parity error indication also is cleared by setting start to 1.

lamp test

When the device is in the hardware reset state, LED_DATA is driven low and LED_CLK runs continuously. This

causes all LEDs to be illuminated and serves as a lamp test function.

multi-LED display

The LED interface is intended to provide the lowest-cost display with a single multifunction LED per port. In

systems requiring a full-feature display using multiple LEDs per port, this is achieved by driving the LEDs directly

from the PHY signals.

RDRAM interface

The TNETX4080 requires the use of external memory devices to retain frame data during switching operations.

The high bandwidth requirements of gigabit-per-second Ethernet switching are met using a concurrent RDRAM

interface (see

Rambus Layout Guide, literature number DL0033).

Each RDRAM interface operates at 600-Mbit/pin/s and is intended for use with 16-/18-/64-/72-Mbit/s concurrent

RDRAMs with access times of 50 ns. The TNETX4080 automatically determines the word length of the

RDRAMs during initialization and performs parity checks if 9-bit memories are in use.

A maximum of 16 RDRAM devices of differing organizations can be attached to any one RDRAM interface.

Multiple devices must be daisy-chained together via their SIN and SOUT pins during initialization (see Figure 5).

All RDRAMs in a given system must be of the same type.

TNETX4080GGP 数据表(PDF) 34 Page - Texas Instruments

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