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TNETX4080GGP 数据表(PDF) 8 Page - Texas Instruments |
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TNETX4080GGP 数据表(HTML) 8 Page - Texas Instruments |
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8 / 64 page  TNETX4080 ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_RXD3 M00_RXD2 M00_RXD1 M00_RXD0 M01_RXD3 M01_RXD2 M01_RXD1 M01_RXD0 M02_RXD3 M02_RXD2 M02_RXD1 M02_RXD0 M03_RXD3 M03_RXD2 M03_RXD1 M03_RXD0 M04_RXD3 M04_RXD2 M04_RXD1 M04_RXD0 M05_RXD3 M05_RXD2 M05_RXD1 M05_RXD0 M06_RXD3 M06_RXD2 M06_RXD1 M06_RXD0 M07_RXD3 M07_RXD2 M07_RXD1 M07_RXD0 D20 C20 B20 A20 D15 C15 B15 A15 D10 C10 B10 A10 D5 C5 B5 A5 K3 K2 K1 J1 R4 R3 R2 R1 Y4 Y3 Y2 Y1 AC7 AD7 AE7 AF7 I Pullup Receive data. Nibble receive data from the attached PHY device. Data on these signals is synchronous to Mxx_RCLK. When Mxx_RXDV and Mxx_RXER are low, these pins are sampled the cycle before Mxx_LINK goes high to configure the port, based on capabilities negotiated by the attached PHY device as follows: – Mxx_RXD0 indicates full-duplex mode when high; half duplex when low, and sets duplex in PortxStatus. – Mxx_RXD1 indicates IEEE Std 802.3 pause frame support when high; no pause when low, and sets pause in PortxStatus. – Mxx_RXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, and sets speed in PortxStatus. – Mxx_RXD3 is unused and is ignored. M00_RXER M01_RXER M02_RXER M03_RXER M04_RXER M05_RXER M06_RXER M07_RXER C19 C14 B9 B4 L4 T3 AA2 AD8 I Pulldown Receive error. Indicates reception of a coding error on received data. M00_TCLK M01_TCLK M02_TCLK M03_TCLK M04_TCLK M05_TCLK M06_TCLK M07_TCLK B23 C17 C13 A8 F1 L2 T1 AD4 I Pullup Transmit clock. Transmit clock source from the attached PHY or PMI device. |
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