TNETX4080GGP datasheet(33/64 Pages) TI1

33 / 64 page

TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

compatibility with future device revisions

All EEPROM locations that correspond to reserved addresses in the memory map, register bits that are read

only, and register bits that are marked as reserved should be set to 0 to ensure compatibility with future versions

of the device. Failure to do so may result in the unintentional activation of features in future devices. All such

bits are included in the CRC calculation.

LED interface

This interface allows a visual status for each port to be displayed. In addition, the state of the internal flow control

and fault functions are displayed along with 12 software-controllable LEDs.

Each port has a single LED, which can convey three states, as shown in Table 9.

Table 9. Port LED States

STATE

DISPLAY

No link

Off

Link, but no activity

Activity

Flashing at 8 Hz

The interface is intended for use in conjunction with external octal shift registers, clocked with LED_CLK. Every

1/16th of a second, the status bits are shifted out via LED_DATA.

The status bits are shifted out in one of two possible orders, as determined by slast in LEDControl, to ensure

that systems that do not require all the LED status can be implemented with the minimum number of octal shift

registers (see Table 10).

D If slast = 0, the software-controlled status bits are shifted out before the port status bits.

D If slast = 1, the software-controlled status bits are shifted out after the port status bits.

The fault status bit is shifted out last, enabling a minimal system that displays only the fault status to be

implemented without any shift registers.

TNETX4080GGP 数据表(PDF) 33 Page - Texas Instruments