TNETX4080GGP datasheet(27/64 Pages) TI1

27 / 64 page

TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MAC interface

receive control

Data received from the PHYs is interpreted and assembled into the TNETX4080 buffer memory. Interpretation

involves detection and removal of the preamble, extraction of the address and frame length, extraction of the

IEEE Std 802.1Q header (if present), and data handling and CRC. Also included is a jabber-detection timer to

detect frames that exceed the maximum length being received on the network.

giant (long) frames

The maxlen bit within each port’s PortxControl register controls the maximum received frame size on that port.

D If maxlen = 0, the maximum received frame length Is 1535 bytes if no VLAN header is inserted, or 1531 bytes

if a VLAN header is inserted. (When stored within the switch, a frame never can be longer than 1535 bytes).

D If maxlen = 1, the maximum received frame length is 1518 bytes as specified by IEEE Std 802.3. This is

the maximum length on the wire. If a VLAN header is inserted into a 1518-byte frame within the MAC, the

frame is stored as a 1522-byte frame within the switch.

All received frames that exceed the maximum length are discarded by the switch.

The long option bit in StatControl indicates how the statistics for long frames should be recorded.

short frames

All received frames less than 64 bytes in length are discarded upon reception and are not stored in memory or

transmitted.

receive filtering of frames

Received frames that contain an error (e.g., CRC, alignment, jabber, etc.) are discarded before transmission

and the relevant statistics counter is updated.

data transmission

The MAC takes data from the TNETX4080 internal buffer memory and passes it to the PHY. The data also is

synchronized to the transmit clock rate.

A CRC block checks that the outgoing frame has not been corrupted within the switch by verifying that it still

has a valid CRC as the frame is being transmitted. If a CRC error is detected, it is counted in the transmit data

errors counter.

transmit control

The frame control block handles the output of data to the PHYs. Several error states are handled. If a collision

is detected, the state machine jams the output. If the collision was late (after the first 64-byte buffer has been

transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While operating

in full duplex, both carrier-sense (CRS) mode and collision-sensing modes are disabled (the switch does not

start transmitting a new frame if collision is active in full-duplex mode).

Internally, frame data only is removed from buffer memory once it has been successfully transmitted without

collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision

is detected, frame recovery and retransmission are initiated.

TNETX4080GGP 数据表(PDF) 27 Page - Texas Instruments

TNETX4080GGP 数据表(HTML) 27 Page - Texas Instruments

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