TNETX4080GGP datasheet(31/64 Pages) TI1

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TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

EEPROM interface

The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfigured

system. This also can be used to change or reconfigure the system and retain the preferences between system

power downs.

The EEPROM contains configuration and initialization information that is accessed infrequently, typically at

power up and after a reset. The organization of the EEPROM data is shown in the DIO address map. Downloads

are initiated in one of two ways:

D At the end of hard reset (rising edge on RESET)

D Writing a 1 to load in SysControl register. This bit is cleared automatically when the download completes.

It cannot be set during the download by the EEPROM data, thereby preventing a download loop.

During the download, no DIO writes are permitted. (If a DIO write is attempted, SRDY is held high until the

download has completed.)

Either a 24C02 or 24C08 serial EEPROM device can be used. Both use a two-wire serial interface for

communication and are available in a small-footprint package.

D The 24C02 provides 2048 bits, organized as 256 × 8. Downloading data from the EEPROM initializes DIO

addresses 0x0000 through 0x00FB. These registers control all initializable functions except VLANs. The

downloading sequence starts with DIO address 0x0000, continuing in ascending order to 0x00FF.

D The 24C08 provides 8192 bits, organized as 1024 × 8. Downloading data from the EEPROM initializes DIO

addresses 0x0000 through 0x03FF. These registers control all initializable functions, including VLANs. The

downloading sequence starts with DIO address 0x0100, continuing in ascending order to 0x03FF, followed

by address 0x0000, and continuing in ascending order to 0x00FF. This ensures that SysControl is the last

The EEPROM size is detected automatically according to the address assigned to the EEPROM:

D 2048 bits, organized as a 256 × 8 EEPROM, should have A0, A1, and A2 pins tied low.

D 8192 bits, organized as a 1024 × 8 EEPROM, should have A0 and A1 pins tied low and A2 pin tied high

(see Figure 4).

24C0x

Flash EEPROM

GND

24C02: GND

24C08: VDD

SCL

SDA

EDIO

ECLK

TNETX4090

Figure 4. Flash EEPROM Configuration

TNETX4080GGP 数据表(PDF) 31 Page - Texas Instruments

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