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TNETX4080GGP 数据表(PDF) 7 Page - Texas Instruments |
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TNETX4080GGP 数据表(HTML) 7 Page - Texas Instruments |
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7 / 64 page  TNETX4080 ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_COL M01_COL M02_COL M03_COL M04_COL M05_COL M06_COL M07_COL C21 D16 C11 A6 H2 N2 V1 AC6 I Pulldown Collision sense. Assertion of Mxx_COL indicates network collision. In full-duplex mode, the port does not start transmitting a new frame if this signal is active; the value of this pin is ignored at all other times. M00_CRS M01_CRS M02_CRS M03_CRS M04_CRS M05_CRS M06_CRS M07_CRS B21 C16 B11 B6 H1 P3 W3 AD6 I Pulldown Carrier sense. Indicates a frame-carrier signal is being received. M00_LINK M01_LINK M02_LINK M03_LINK M04_LINK M05_LINK M06_LINK M07_LINK B19 B14 A9 A4 L3 T2 AA1 AF3 I Pulldown Connection status. Indicates the presence of port connection: – If Mxx_LINK = 0, there is no link. – If Mxx_LINK = 1, the link is OK. An internal pullup resistor is provided. M00_RCLK M01_RCLK M02_RCLK M03_RCLK M04_RCLK M05_RCLK M06_RCLK M07_RCLK A21 B16 A11 C6 J3 P2 W2 AE6 I Pullup Receive clock. Receive clock source from the attached PHY device. M00_RENEG M01_RENEG M02_RENEG M03_RENEG M04_RENEG M05_RENEG M06_RENEG M07_RENEG C26 D26 D1 C1 F3 F2 AA3 AD1 I None Renegotiate. Indicates to the attached PHY that this port wishes to renegotiate a new configuration. M00_RXDV M01_RXDV M02_RXDV M03_RXDV M04_RXDV M05_RXDV M06_RXDV M07_RXDV D19 A16 C9 C4 J2 T4 W1 AC8 I Pulldown Receive data valid. Indicates data on Mxx_RXD7–Mxx_RxD0. is valid. This signal is synchronous to Mxx_RCLK. |
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