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MMPF0100 数据表(PDF) 41 Page - Freescale Semiconductor, Inc |
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MMPF0100 数据表(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 136 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 41 PF0100 Functional Block Requirements and Behaviors Power Generation SW1A/B/C Single Phase In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers, respectively. Figure 10 shows the connection for SW1A/B/C in single phase mode. During Single Phase mode operation, all three phases will use the same configuration for frequency, phase, and DVS speed set in SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should be used. The SW1FB pin should be left floating in this configuration. Driver Controller SW1AIN SW1ALX SW1FB ISENSE COSW1A CINSW1A LSW1 I2C Interface GNDSW1A SW1A/B/C SW1AMODE SW1AFAULT VIN Driver Controller SW1BIN SW1BLX ISENSE CINSW1B GNDSW1B SW1BMODE SW1BFAULT VIN EA Z1 Z2 Internal Compensation VREF DAC I2C Driver Controller EA Z1 Z2 Internal Compensation SW1CIN SW1CLX SW1CFB ISENSE CINSW1C GNDSW1C SW1CMODE SW1CFAULT VREF DAC I2C VIN Figure 10. SW1A/B/C Single Phase Block Diagram |
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