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MMPF0100 数据表(PDF) 9 Page - Freescale Semiconductor, Inc

部件名 MMPF0100
功能描述  14 Channel Configurable Power Management Integrated Circuit
PDF  136 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MMPF0100 数据表(HTML) 9 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
PF0100
Pin Connections
Pin Definitions
23
SW2IN
I
4.8 V
Analog
Input to SW2 regulator. Connect pin 23 together with pin 24 and
bypass with at least a 4.7
μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to these pins as possible.
24
SW2IN
I
4.8 V
Analog
25
SW2FB
I
3.6 V
Analog
Output voltage feedback for SW2. Route this trace separately
from the high current path and terminate at the output
capacitance.
26
VGEN3
O
3.6 V
Analog
VGEN3 regulator output. Bypass with a 2.2
μF ceramic output
capacitor.
27
VIN2
I
3.6 V
Analog
VGEN3,4 input. Bypass with a 1.0
μF decoupling capacitor as
close to the pin as possible.
28
VGEN4
O
3.6 V
Analog
VGEN4 regulator output, Bypass with a 4.7
μF ceramic output
capacitor.
29
VHALF
I
3.6 V
Analog
Half supply reference for VREFDDR
30
VINREFDDR
I
3.6 V
Analog
VREFDDR regulator input. Bypass with at least 1.0
μF decoupling
capacitor as close to the pin as possible.
31
VREFDDR
O
3.6 V
Analog
VREFDDR regulator output
32
SW3VSSSNS
GND
-
GND
Ground reference for the SW3 regulator. Connect to GNDREF
externally via the board ground plane.
33
SW3BFB
I
3.6 V
Analog
Output voltage feedback for SW3B. Route this trace separately
from the high current path and terminate at the output
capacitance.
34
SW3BIN
I
4.8 V
Analog
Input to SW3B regulator. Bypass with at least a 4.7
μF ceramic
capacitor and a 0.1
μF decoupling capacitor as close to the pin as
possible.
35
SW3BLX
O
4.8 V
Analog
Regulator 3B switch node connection
36
SW3ALX
O
4.8 V
Analog
Regulator 3A switch node connection
37
SW3AIN
I
4.8 V
Analog
Input to SW3A regulator. Bypass with at least a 4.7
μF ceramic
capacitor and a 0.1
μF decoupling capacitor as close to the pin as
possible.
38
SW3AFB
I
3.6 V
Analog
Output voltage feedback for SW3A. Route this trace separately
from the high current path and terminate at the output
capacitance.
39
VGEN5
O
3.6 V
Analog
VGEN5 regulator output. Bypass with a 2.2
μF ceramic output
capacitor.
40
VIN3
I
4.8 V
Analog
VGEN5, 6 input. Bypass with a 1.0
μF decoupling capacitor as
close to the pin as possible.
41
VGEN6
O
3.6 V
Analog
VGEN6 regulator output. By pass with a 2.2
μF ceramic output
capacitor.
42
LICELL
I/O
3.6 V
Analog
Coin cell supply input/output
43
VSNVS
O
3.6 V
Analog
LDO or coin cell output to processor
44
SWBSTFB
I
4.8 V
Analog
Boost regulator feedback. Connect this pin to the output rail close
to the load. Keep this trace away from other noisy traces and
planes.
45
SWBSTIN
I
4.8 V
Analog
Input to SWBST regulator. Bypass with at least a 2.2
μF ceramic
capacitor and a 0.1
μF decoupling capacitor as close to the pin as
possible.
Table 3. PF0100 Pin Definitions (continued)
Pin Number
Pin Name
Pin
Function
Max Rating
Type
Definition



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