MMPF0100 datasheet(16/136 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

PF0100

General Description

Functional Block Diagram

6.2

Functional Block Diagram

Logic and Control

Switching Regulators

SW1A/B/C

(0.3 to 1.875V)

Configurable 4.5A or

2.5A+2.0A

Linear Regulators

SW2

(0.4 to 3.3V, 2A)

SW3A/B (2.5A)

(0.4 to 3.3V)

Configurable 2.5A or

1.25A+1.25A

SW4

(0.4 to 3.3V, 1A)

Boost Regulator

(5 to 5.15V, 600mA)

USB OTG Supply

VGEN1

(0.8 to 1.55V, 100mA)

VGEN2

(0.8 to 1.55V, 250mA)

VGEN3

(1.8 to 3.3V, 100mA)

VGEN4

(1.8 to 3.3V, 350mA)

VGEN5

(1.8 to 3.3V, 100mA)

VGEN6

(1.8 to 3.3V, 200mA)

Bias & References

Parallel MCU Interface

Regulator Control

VSNVS

(1.0 to 3.0V, 400uA)

RTC supply with coin cell

charger

MMPF0100 Functional Internal Block Diagram

I2C Communication & Registers

Power Generation

Fault Detection and Protection

DDR Voltage Reference

Current Limit

Short-Circuit

Internal Core Voltage Reference

Thermal

OTP Startup Configuration

Sequence and

timing

OTP Prototyping

(Try before buy)

Voltage

Power stage

Figure 4. Functional Block Diagram

6.3

Functional Description

6.3.1

Power Generation

The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs,

one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral

devices.

The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with

higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current

demands. Further, SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the

buck regulators, SW4, can also operate as a tracking regulator when used for memory termination. The buck regulators provide

the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to

allow controlled supply rail adjustments for the processor cores and/or other circuitry.

Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the

main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A

specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or

without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on

the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.

6.3.2

Control Logic

The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing

including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-

up section, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP

configuration.

The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures

supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger

for the coin cell is included as well.

MMPF0100 数据表(PDF) 16 Page - Freescale Semiconductor, Inc

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