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MMPF0100 数据表(PDF) 106 Page - Freescale Semiconductor, Inc |
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MMPF0100 数据表(HTML) 106 Page - Freescale Semiconductor, Inc |
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106 / 136 page  Analog Integrated Circuit Device Data 106 Freescale Semiconductor PF0100 Functional Block Requirements and Behaviors Control Interface I2C Block Description A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127. SW1CFAULTI SW1CFAULTM SW1CFAULTS Regulator 1C over-current limit Sense is 1 if above current limit L to H 8.0 SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 over-current limit Sense is 1 if above current limit L to H 8.0 SW3AFAULTI SW3AFAULTM SW3AFAULTS Regulator 3A over-current limit Sense is 1 if above current limit L to H 8.0 SW3BFAULTI SW3BFAULTM SW3BFAULTS Regulator 3B over-current limit Sense is 1 if above current limit L to H 8.0 SW4FAULTI SW4FAULTM SW4FAULTS Regulator 4 over-current limit Sense is 1 if above current limit L to H 8.0 SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST over-current limit Sense is 1 if above current limit L to H 8.0 VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS VGEN2 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS VGEN3 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS VGEN4 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS VGEN5 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS VGEN6 over-current limit Sense is 1 if above current limit L to H 8.0 OTP_ECCI OTP_ECCM OTP_ECCS 1 or 2 bit error detected in OTP registers Sense is 1 if error detected L to H 8.0 Notes 67. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0]. Table 116. Register INTSTAT0 - ADDR 0x05 Name Bit # R/W Default Description PWRONI 0 R/W1C 0 Power on interrupt bit LOWVINI 1 R/W1C 0 Low-voltage interrupt bit THERM110I 2 R/W1C 0 110 °C Thermal interrupt bit THERM120I 3 R/W1C 0 120 °C Thermal interrupt bit THERM125I 4 R/W1C 0 125 °C Thermal interrupt bit THERM130I 5 R/W1C 0 130 °C Thermal interrupt bit UNUSED 7:6 – 00 Unused Table 115. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Trigger Debounce Time (ms) |
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