SPC56AP54X datasheet(58/104 Pages) STMICROELECTRONICS

58 / 104 page

Electrical characteristics

SPC56xP54x, SPC56xP60x

58/104

Doc ID 18340 Rev 3

3.6

Electromagnetic interference (EMI) characteristics

3.7

Electrostatic discharge (ESD) characteristics

3.8

Power management electrical characteristics

3.8.1

Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast to be connected as shown in

Figure 9. Table 16 contains all approved NPN ballast components. Capacitances should be

placed on the board as near as possible to the associated pins. Care should also be taken

to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than

LReg, see Table 17.

Note:

The voltage regulator output cannot be used to drive external circuits. Output pins are used

only for decoupling capacitances.

VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is not

possible to provide VDD_LV_COR through external regulator.

For the SPC56xP54/60 microcontroller, capacitors, with total values not below CDEC1,

should be placed between VDD_LV_CORx/VSS_LV_CORx close to external ballast transistor

emitter. 4 capacitors, with total values not below CDEC2, should be placed close to

microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the

Table 14.

EMI testing specifications

Parameter

Symbol

Conditions

fOSC/fBUS

Frequency

Level

(Max)

Unit

VRE_TEM

Radiated

emissions,

electric field

VDD =5V;

TA =25°C

150 kHz–30 MHz

RBW 9 kHz, Step

Size 5 kHz

30 MHz–1 GHz

RBW 120 kHz,

Step Size 80 kHz

8 MHz crystal

64 MHz bus

No PLL frequency

modulation

150 kHz–150 MHz

V

150–1000 MHz

IEC Level

—

8 MHz crystal

64 MHz bus

±2% PLL

frequency

modulation

150 kHz–150 MHz

V

150–1000 MHz

IEC Level

—

Table 15.

ESD ratings(1),(2)

Symbol

Parameter

Conditions

Value

Unit

VESD(HBM)

SR Electrostatic discharge (Human Body Model)

—

2000

VESD(CDM)

SR Electrostatic discharge (Charged Device Model)

—

750 (corners)

500 (other)

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at

room temperature followed by hot temperature, unless specified otherwise in the device specification

SPC56AP54X 数据表(PDF) 58 Page - STMicroelectronics

SPC56AP54X 数据表(HTML) 58 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载