SPC56AP54X datasheet(11/104 Pages) STMICROELECTRONICS

11 / 104 page

SPC56xP54x, SPC56xP60x

Introduction

Doc ID 18340 Rev 3

11/104

Table 4.

SPC56xP54/60 series block summary

Block

Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Block of read-only memory containing VLE code which is executed according to

the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Controller area network

(FlexCAN)

Supports the standard CAN communications protocol

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus

width.

Cyclic redundancy checker

(CRC) unit

Is dedicated to the computation of CRC off-loading the CPU. Each context has

a separate CRC computation engine in order to allow the concurrent

computation of the CRC of multiple data streams.

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Enhanced direct memory access

(eDMA)

Performs complex data transfers with minimal intervention from a host

processor via “n” programmable channels

Enhanced timer (eTimer)

Provides enhanced programmable up/down modulo counting

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection and control unit

(FCCU)

Provides functional safety to the device

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexRay (FlexRay communication

controller)

Provides high-speed distributed control for advanced automotive applications

Frequency-modulated phase-

locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

JTAG controller

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

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