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SPC56AP54X 数据表(PDF) 60 Page - STMicroelectronics |
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SPC56AP54X 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 104 page  Electrical characteristics SPC56xP54x, SPC56xP60x 60/104 Doc ID 18340 Rev 3 3.8.2 Voltage monitor electrical characteristics The device implements a Power On Reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while device is supplied: ● POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state ● LVDHV3 monitors VDD to ensure device reset below minimum functional supply ● LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range ● LVDLVCOR monitors low voltage digital power domain Table 17. Voltage regulator electrical characteristics Symbol C Parameter Conditions Value Unit Min Typ Max VDD_LV_REGCOR CC P Output voltage under maximum load run supply current configuration Post-trimming 1.15 — 1.32 V CDEC1 SR — External decoupling/stability ceramic capacitor BJT from Table 16. 3 capacitances (i.e. X7R or X8R capacitors) with nominal value of 10 µF 19.5 30 — µF BJT BC817, one capacitance of 22 µF 14.3 22 µF RREG SR — Resulting ESR of all three capacitors of CDEC1 BJT from Table 16. 3x10 µF. Absolute maximum value between 100 kHz and 10 MHz —— 50 m Resulting ESR of the unique capacitor CDEC1 BJT BC817, 1x 22 µF. Absolute maximum value between 100 kHz and 10 MHz 10 — 40 m CDEC2 SR — External decoupling/stability ceramic capacitor 4 capacitances (i.e. X7R or X8R capacitors) with nominal value of 440 nF 1200 1760 — nF CDEC3 SR — External decoupling/stability ceramic capacitor on VDD_HV_REG 3 capacitances (i.e. X7R or X8R capacitors) with nominal value of 10 µF; CDEC3 has to be equal or greater than CDEC1 19.5 30 — µF LReg SR — Resulting ESL of VDD_HV_REG, BCTRL and VDD_LV_CORx pins —— — 15 nH |
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