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SPC56AP54X 数据表(PDF) 74 Page - STMicroelectronics

部件名 SPC56AP54X
功能描述  32-bit Power Architecture® based MCU with 1088 KB Flash memory and 80 KB RAM for automotive chassis and safety applications
PDF  104 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

SPC56AP54X 数据表(HTML) 74 Page - STMicroelectronics

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Electrical characteristics
SPC56xP54x, SPC56xP60x
74/104
Doc ID 18340 Rev 3
3.14
16 MHz RC oscillator electrical characteristics
3.15
Analog-to-Digital converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital
Converter.
2.
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
3.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
4.
fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
5.
This value is determined by the crystal manufacturer and board design.
6.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
7.
Proper PC board layout procedures must be followed to achieve specifications.
8.
Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER
and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
9.
Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
11. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
12. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
13. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 31.
16 MHz RC oscillator electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fRC
P
RC oscillator frequency
TA = 25 °C
16
MHz
RCMVAR
P
Fast internal RC oscillator variation
over temperature and
supply with respect to f
RC at TA = 25 °C
in high-frequency configuration
—–6
6
%
RCMTRIM
T
Post Trim Accuracy: The variation of
the PTF(1) from the 16 MHz
TA = 25 °C
–1
1
%
RCMSTEP
T
Fast internal RC oscillator trimming
step
TA = 25 °C
1.6
%
1.
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature



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