SPC56AP54X datasheet(69/104 Pages) STMICROELECTRONICS

69 / 104 page

SPC56xP54x, SPC56xP60x

Electrical characteristics

Doc ID 18340 Rev 3

69/104

Table 23.

Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Symbol

Parameter

Conditions

Value

Unit

Typ

Max

IDD_LV_CORE

Supply

current

RUN — Maximum Mode(1)

VDD_LV_CORE

externally forced at

1.3 V

ADC Freq = 32 MHz

PLL Freq = 64 MHz

64 MHz

120

RUN - Platform consumption,

single core(2)

VDD_LV_CORE

externally forced to 1.3V

16 MHz

40 MHz

64 MHz

RUN - Platform consumption,

dual core(3)

16 MHz

40 MHz

64 MHz

RUN — Maximum Mode(4)

VDD_LV_CORE

externally forced at

1.3 V

64 MHz

113

HALT Mode(5)

VDD_LV_CORE

externally forced at

1.3 V

—5.5

STOP Mode(6)

VDD_LV_CORE

externally forced at

1.3 V

—4.5

IDD_FLASH

Flash memory supply current

during read

VDD_HV_FL at 3.3 V

—

Flash memory supply current

during erase operation on 1

flash memory module

VDD_HV_FL at 3.3 V

—

IDD_ADC

ADC supply current —

Maximum Mode

VDD_HV_AD at 3.3 V

ADC Freq = 16 MHz

—3

IDD_OSC

OSC supply current

VDD_OSC at 3.3 V

8 MHz

2.4

Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz

on, PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,

PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in

power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL

are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

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