M24LR04E-R datasheet(32/142 Pages) STMICROELECTRONICS

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I2C device operation

M24LR04E-R

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Doc ID 022208 Rev 5

5.5.1

I²C timeout on Start condition

I²C communication with the M24LR04E-R starts with a valid Start condition, followed by a

device select code.

If the delay between the Start condition and the following rising edge of the Serial Clock

(SCL) that samples the most significant of the Device Select exceeds the tSTART_OUT time

(see Table 122), the I²C logic block is reset and further incoming data transfer is ignored

until the next valid Start Condition.

Figure 7.

I²C timeout on Start condition

5.5.2

I²C timeout on clock period

During data transfer on the I²C bus, the serial clock high pulse width High (tCHCL) or serial

clock pulse width Low (tCLCH) exceeds the maximum value specified in Table 122, the I²C

logic block is reset and any further incoming data transfer is ignored until the next valid Start

condition.

5.6

Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 2 (on Serial Data (SDA), most significant bit first).

Only one memory device can be connected on a single I²C bus. In M24LR04E-R, E1 and E0

are internally set to 1.

The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 18.

Operating modes

Mode

RW bit

Bytes

Initial sequence

Current address read

Start, device select, RW = 1

Random address read

Start, device select, RW = 0, address

reStart, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

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