M24LR04E-R datasheet(36/142 Pages) STMICROELECTRONICS

部件名	M24LR04E-R

功能描述	4-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz

PDF	142 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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36 / 142 page

I2C device operation

M24LR04E-R

36/142

Doc ID 022208 Rev 5

5.10

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is

shown in Table 122, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

The sequence, as shown in Figure 10, is:

Initial condition: a write cycle is in progress.

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus

master goes back to Step 1. If the device has terminated the internal write cycle, it

responds with an Ack, indicating that the device is ready to receive the second part of

the instruction (the first byte of this instruction having been sent during Step 1).

M24LR04E-R 数据表(PDF) 36 Page - STMicroelectronics