AD9854SLASHPCB datasheet(31/44 Pages) AD

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AD9854

–31–

REV. 0

Power-Down Functions

Four bits are available to power down the AD9854. Each bit is

active high, that is, they default low and a Logic 1 causes the

power-down function to be working, The four bits all reside in

the same control byte such that one IO write cycle can complete

a full power-down by writing all four bits true simultaneously.

The four bits are located in Control Register [28, 26:24] and

are described below. The default state for these bits is Logic 0,

inactive.

CR[31:29] are open.

CR[28] is the comparator power-down bit. When set (Logic 1),

this signal indicates to the comparator that a power-down mode

is active. This bit is an output of the digital section and is an

input to the analog section.

CR[27] must always be written to logic zero. Writing this bit to

Logic 1 causes the AD9854 to stop working until a master

reset is applied.

CR[26] is the Q DAC power-down bit. When set (Logic 1), this

signal indicates to the Q DAC that a power-down mode is active.

CR[25] is the full DAC power-down bit. When set (Logic 1),

this signal indicates to both the I and Q DACs as well as the refer-

ence that a power-down mode is active.

CR[24] is the digital power-down bit. When set (Logic 1), this

signal indicates to the digital section that a power-down mode is

active. Within the digital section, the clocks will be forced to dc,

effectively powering down the digital section. The REFCLK

input will still be seen by the PLL and the PLL will continue to

output the higher frequency.

REFCLK Multiplier PLL Functions

Seven control register bits, located in the Control Register

[22:16] positions, relate to the PLL.

CR[23] is reserved. Write to zero.

CR[22] is the PLL range bit. The PLL range bit controls the

VCO gain. The power-up state of the PLL range bit is Logic 1,

higher gain for frequencies above 200 MHz.

CR[21] is the bypass PLL bit, active high. When active, the PLL

is powered down and the REFCLK input is used to drive the

system clock signal. The power-up state of the bypass PLL bit is

Logic 1, PLL bypassed.

CR[20:16] bits are the PLL multiplier factor. These bits are the

REFCLK multiplication factor unless the bypass PLL bit is set.

The PLL multiplier valid range is from 4 to 20, inclusive.

Other Operational Functions

CR[15] is the clear accumulator 1 bit. This bit has a one-shot

type function. When written active, Logic 1, a clear accumulator

1 signal is sent to the DDS logic, resetting the accumulator value to

zero. The bit is then automatically reset, but the buffer memory

is not reset. This bit allows the user to easily create a sawtooth

frequency sweep pattern with very little (or no) user input

required. This bit is intended for chirp mode only, but there is

no logic to suppress its functionality in other modes.

CR[14] is the clear accumulator bit. This bit, active high, holds

both the accumulator 1 and accumulator 2 values at zero for as

long as the bit is active. This allows the DDS phase to be initial-

ized via the I/O port.

CR[13] is the triangle bit. When this bit is set, the AD9854 will

automatically perform a continuous frequency sweep from F1 to

F2 frequencies and back. The effect is a triangular frequency

sweep. When this bit is set, the operating mode must be set to

ramped FSK.

CR[12] is the source Q DAC bit on the AD9854 only. When

set, the Q path DAC accepts data from the QDAC Register.

For the AD9854, this bit does not require a Logic 1 as the only

data available to the Q path DAC is from the QDAC Register.

CR[11:9] are the three bits that describe the ﬁve operating modes

of the AD9854:

0h = Single-Tone Mode

1h = FSK Mode

2h = Ramped FSK mode

3h = Chirp Mode

4h = PSK Mode

CR[8] is the internal update active bit. When this bit is set to

Logic 1, the I/O UD pin is an output and the AD9854 generates

the I/O UD signal. When Logic 0, external I/O UD functionality

is performed, the I/O UD pin is conﬁgured as an input.

CR[7] is reserved. Write to zero.

CR[6] is the bypass of the inverse sinc ﬁlter bit. When set, the

data from the DDS block goes directly to the output shaped-

keying logic and the clock to the inverse sinc ﬁlter is stopped.

Default is clear, ﬁlter enabled.

CR[5] is the shaped keying enable bit. When set the output

ramping function is enabled and is performed in accordance with

the CR[4] bit requirements.

CR[4] is the internal/external output shaped-keying control

bit. When set Logic 1, the shaped-keying factor will be inter-

nally generated and applied to both the I and Q paths. When

clear, the output shaped-keying function is externally controlled

by the user and the shaped-keying factor is the I and Q output

shaped-keying factor register values. Defaults low external shaped-

keying factors used. The two registers that are the shaped-keying

factors also default low such that the output is off at power-up

and until the device is programmed by the user.

CR[3:2] are reserved. Write to zero.

CR[1] is the serial port MSB/LSB ﬁrst bit. Defaults low, MSB

ﬁrst.

CR[0] is the serial port SDO active bit. Defaults low, inactive.

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