AD9854SLASHPCB datasheet(20/44 Pages) AD

20 / 44 page

AD9854

–20–

REV. 0

MODE

TW1

TW2

FSK DATA

TRIANGLE

BIT

010 (RAMPED FSK)

Figure 40. Effect of Triangle Bit in Ramped FSK Mode

Generally speaking, the Delta Frequency Word will be a much

smaller value as compared to that of the F1 or F2 tuning word.

For example, if F1 and F2 are 1 kHz apart at 13 MHz, the

Delta Frequency Word might be only 25 Hz.

Figure 41 shows that premature toggling causes the ramp to

immediately reverse itself and proceed at the same rate and resolu-

tion back to originating frequency.

MODE

TW1

TW2

FSK DATA

TRIANGLE BIT

000 (DEFAULT)

010 (RAMPED FSK)

Figure 42. Automatic Linear Ramping Using the Triangle Bit

The control register contains a Triangle bit at parallel register

address 1F hex. Setting this bit high in Mode 010 causes an

automatic ramp-up and ramp-down between F1 and F2 to occur

without having to toggle Pin 29 as shown in Figure 40. In fact,

the logic state of Pin 29 has no effect once the Triangle bit is set

high. This function uses the ramp-rate clock time period and

the delta-frequency-word step size to form a continuously sweeping

linear ramp from F1 to F2 and back to F1 with equal dwell times

at every frequency. Using this function, one can automatically

sweep from dc to the Nyquist limit or any other two frequencies

between dc and Nyquist.

MODE

TW1

TW2

FSK DATA

000 (DEFAULT)

010 (RAMPED FSK)

Figure 41. Effect of Premature Ramped FSK Data

AD9854/PCB 数据表(PDF) 20 Page - Analog Devices

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