AD9854SLASHPCB datasheet(35/44 Pages) AD

35 / 44 page

AD9854

–35–

REV. 0

EVALUATION BOARD

An evaluation board is available that supports the AD9854 DDS

devices. This evaluation board consists of a PCB, software, and

documentation to facilitate bench analysis of the performance of

the AD9854 device. It is recommended that users of the AD9854

familiarize themselves with the operation and performance

capabilities of the device with the evaluation board. The evaluation

board should also be used as a PCB reference design to ensure

optimum dynamic performance from the device.

OPERATING INSTRUCTIONS

To assist in proper placement of the pin-header shorting-jumpers,

the instructions will refer to direction (left, right, top, bottom)

as well as header pins to be shorted. Pin #1 for each three pin-

header has been marked on the PCB corresponding with the

schematic diagram. When following these instructions, position

the PCB so that the text can be read from left to right. The

board is shipped with the pin-headers conﬁguring the board

as follows:

1. REFCLK for the AD9854 is conﬁgured as differential. The

differential clock signals are provided by the 100LVEL16

differential receiver.

2. Input clock for the 100LVEL16 is single-ended via J5. This

signal may be 3.3 V CMOS or a 2 V p-p sine wave capable of

driving 50

Ω (R8).

3. Both DAC outputs from the AD9854 are routed through

the two 120 MHz elliptical LP ﬁlters and their outputs con-

nected to J3 (Q) and J4 (I).

4. The board is set up for software control via the printer port

connector.

5. Conﬁgured for AD9854 operation.

Load the software from the CD onto the host PC’s hard disk.

Only Windows 9X and NT operating system are supported.

Connect a printer cable from the PC to the AD9854 Evaluation

Board printer port connector labeled “J11.”

Attach power wires to connector labeled “TB1” using the screw-

down terminals. This is a plastic connector that press-ﬁts over a

4-pin header soldered to the board. Table IX below shows con-

nections to each pin. DUT = “device under test.”

Table IX. Power Requirements for DUT Pins

AVDD 3.3 V

DVDD 3.3 V

VCC 3.3 V

Ground

for All DUT

for All Other

—for All

Analog Pins

Digital Pins

Devices

Attach REFCLK

There are three possibilities to choose from:

1. On-Board (But Optional) Crystal Clock Oscillator, Y1.

Insert an appropriate 3.3 V CMOS clock oscillator. See that

the shorting jumper at W5 is located on Pins 1 and 2 (the left

two pins). This routes the single-ended oscillator output to a

very high speed “Differential Receiver” (the MC100LVEL16),

where the signal is transformed to a differential PECL output.

To route the differential output signals to AD9854, two more

switches must be conﬁgured. W9 must have a shorting jumper

on Pins 2 and 3 (the right two pins). To engage the differen-

tial clocking mode of the AD9854 W3, Pins 2 and 3 (the right

two pins) must be connected with a shorting jumper.

2. External Differential Clock Input, J5.

This is actually just another single-ended input that will be

routed to the MC100LVEL16 for conversion to differential

PECL output. This is accomplished by attaching a 2 V p-p

clock or sine wave source to J5. Note that this is a 50

Ω

impedance point set by R8. The input signal will be ac-coupled

and then biased to the center switching threshold of the

MC100LVEL16. Position the shorting jumper of W5 to Pins

2 and 3 (the right two pins) to route the signal at J5 to the

differential receiver IC. To route the differential output signals

to AD9854, two more switches must be conﬁgured. W9 must

have a shorting jumper on Pins 2 and 3 (the right two pins).

To engage the differential clocking mode of the AD9854

W3, Pins 2 and 3 (the right two pins) must be connected

with a shorting jumper.

3. External Single-Ended Clock Input, J7.

This mode bypasses the MC100LVEL16 and directly drives

the AD9854 with your reference clock. Attach a 50

Ω, 2 V p-p

sine source that is dc offset to 1.65 V, or a 50

Ω CMOS-level

clock source to J7. Remove the shorting jumper from W5

altogether to make certain that the device (U3) Is not Toggling

or Self-Oscillating. Set the shorting jumper at W9 on Pins

1 and 2 (the left two pins) to route the REFCLK signal from

J7 to Pin 69 of the AD9854. Finally, set the shorting jumper at

W3 to Pins 1 and 2 (the left two pins) to place the AD9854 in

the single-ended clock mode.

Regardless of the origination, the signals arriving at the AD9854

are called the Reference Clock. If you choose to engage the

on-chip REFCLK Multiplier, this signal is the reference clock

for the REFCLK Multiplier and the REFCLK Multiplier output

becomes the SYSTEM CLOCK. If you choose to bypass the

REFCLK Multiplier, the reference clock that you have supplied

is directly operating the AD9854 and is, therefore, the system

clock.

Three-state control or switch headers W11, W12, W14, and

W15 must be shorted to allow the provided software to control

the AD9854 evaluation board via the printer port connector J11.

If programming of the AD9854 is not to be provided by the host

PC via the ADI software, then headers W11, W12, W14, and W15

should be opened (shorting jumpers removed). This effectively

detaches the PC interface and allows the 40-pin header, J10, to

assume control without bus contention. Input signals on J10 going

to the AD9854 should be 3.3 V CMOS logic levels.

Low-Pass Filter Testing

The purpose of 2-pin headers W7 and W10 (associated with J1

and J2) are to allow the two 50

Ω, 120 MHz ﬁlters to be tested

during PCB assembly without interference from other circuitry

attached to the ﬁlter inputs. Normally, a shorting jumper will be

attached to each header to allow the DAC signals to be routed to the

ﬁlters. If the user wishes to test the ﬁlters, the shorting jumpers

at W7 and W10 should be removed and 50

Ω test signals applied

at J1 and J2 inputs to the 50

Ω elliptic ﬁlters. User should refer

to Figure 62 and the following sections to properly position the

remaining shorting jumpers.

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