AD9854

–15–

REV. 0

Next, the transition time from zero-scale to full-scale must

be programmed. The transition time is a function of two fixed

elements and one variable. The variable element is the program-

mable 8-bit RAMP RATE COUNTER. This is a down-counter

being clocked at the system clock rate (300 MHz max) that out-

puts one pulse whenever the counter reaches zero. This pulse is

routed to a 12-bit counter that increments one LSB for every

pulse received. The outputs of the 12-bit counter are connected

to the 12-bit digital multiplier. When the digital multiplier has a

value of all zeros at its inputs, the input signal is multiplied

by zero, producing zero-scale. When the multiplier has a value

of all ones, the input signal is multiplied by a value of one, pro-

ducing full-scale. There are 4094 remaining fractional multiplier

values that will produce output amplitudes corresponding to

their binary values.

The two fixed elements are the clock period of the system clock,

which drives the Ramp Rate Counter, and the 4096 amplitude

steps between zero-scale and full-scale. To give an example,

assume that the System Clock of the AD9854 is 100 MHz (10 ns

period). If the Ramp Rate Counter is programmed for a minimum

count of five, it will take two system clock periods (one rising

edge loads the count-down value, the next edge decrements the

counter from five to four). The relationship of the 8-bit count-

down value to the time period between output pulses is given as:

(N+1)

× SYSTEM CLOCK PERIOD,

where N is the 8-bit count-down value. It will take 4096 of these

pulses to advance the 12-bit up-counter from zero-scale to full-

scale. Therefore, the minimum shaped keying ramp time for a

100 MHz system clock is 4096

× 6 × 10 ns = approximately 246 µs.

The maximum ramp time will be 4096

× 256 × 10 ns = approxi-

mately 10.5

µs.

Finally, changing the logic state of Pin 30, “shaped keying” will

automatically perform the programmed output envelope functions

when OSK INT is high. A logic high on Pin 30 causes the out-

puts to linearly ramp up to full-scale amplitude and hold until

the logic level is changed to low, causing the outputs to ramp

down to zero-scale.

I and Q DACs

The 300 MSPS (maximum) sine and cosine wave outputs of the

DDS. Their maximum output amplitudes are set by the DAC

full-scale maximum output of 20 mA; however, a nominal 10 mA

12-BIT DIGITAL

MULTIPLIER

12

12

(BYPASS MULTIPLIER)

OSK EN = 0

OSK EN = 1

OSK EN = 0

OSK EN = 1

12

12

DIGITAL

SIGNAL IN

USER PROGRAMMABLE

12-BIT Q-CHANNEL

MULTIPLIER

"OUTPUT SHAPE

KEY Q MULT"

REGISTER

12

OSK EN = 1

OSK EN = 0

1

8-BIT DOWN-

COUNTER

SYSTEM

CLOCK

SHAPING

KEYING PIN

SINE DAC

12-BIT

COUNTER

Figure 32. Block diagram of Q-pathway of the digital multiplier section responsible for Shaped Keying function.

The I-pathway is similar, except that no alternate 12-bit Q-DAC source register is provided.

output current provides best spurious-free dynamic range (SFDR)

amps. DAC output compliance specification limits the maximum

voltage developed at the outputs to –0.5 V to +1 V. Voltages

developed beyond this limitation will cause excessive DAC

distortion and possibly permanent damage. The user must choose

a proper load impedance to limit the output voltage swing to

the compliance limits. Both DAC outputs should be terminated

equally for best SFDR, especially at higher output frequencies

where harmonic distortion errors are more prominent.

Both DACs are preceded by inverse SIN(x)/x filters (a.k.a. inverse

sinc filters) that precompensate for DAC output amplitude varia-

tions over frequency to achieve flat amplitude response from dc

to Nyquist. Digital multipliers follow the inverse sinc filters to

allow amplitude control, amplitude modulation and amplitude

shaped keying. The inverse sinc filters (address 20 hex, Bypass

Inv Sinc bit)) and digital multipliers (address 20 hex, OSK EN

bit) can be bypassed for power conservation by setting those bits

high. Both DACs can be powered down by setting the DAC PD

bit high (address 1D of control register) when not needed.

I-DAC outputs are designated as IOUT1 and IOUT1B, Pins

48 and 49 respectively. Q-DAC outputs are designated as IOUT2

AND IOUT2B, Pins 52 and 51 respectively.

Control DAC

The 12-bit Q DAC can be reconfigured to perform as a “control”

or auxiliary DAC. The control DAC output can provide dc

control levels to external circuitry, generate ac signals, or enable

duty cycle control of the on-board comparator. When the SRC

QDAC bit in control register (parallel address 1F hex) is set

high, the Q DAC inputs are switched from internal 12-bit Q

data source (default setting) to external 12-bit, twos-complement

data, supplied by the user. Data is channeled through the serial or

parallel interface to the 12-bit Q DAC register (address 26 and 27

hex) at a maximum 100 MHz data rate. This DAC is clocked at

the system clock, 300 MSPS (maximum), and has the same maxi-

mum output current capability as that of the I DAC. The single

for both DACs. The control DAC can be separately powered

down for power conservation when not needed by setting the

Q DAC POWER-DOWN bit high (address 1D hex). Control

DAC outputs are designated as IOUT2 and IOUT2B (Pins 52

and 51 respectively).