AD9854SLASHPCB datasheet(14/44 Pages) AD

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AD9854

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architecture allows the generation of simultaneous quadrature out-

puts at frequencies up to 150 MHz, which can be digitally tuned

at a rate of up to 100 million new frequencies per second. The

(externally ﬁltered) sine wave output can be converted to a

square wave by the internal comparator for agile clock generator

applications. The device provides 14 bits of digitally-controlled

phase modulation and single-pin PSK. The on-board 12-bit I

and Q DACs, coupled with the innovative DDS architecture,

provide excellent wideband and narrowband output SFDR. The

Q-DAC can also be conﬁgured as a user-programmable control

DAC if the quadrature function is not desired. When conﬁgured

with the on-board comparator, the 12-bit control DAC facilitates

static duty cycle control in the high-speed clock generator appli-

cations. Two 12-bit digital multipliers permit programmable

amplitude modulation, shaped on/off keying and precise ampli-

tude control of the quadrature outputs. Chirp functionality is

also included which facilitates wide bandwidth frequency

sweeping applications. The AD9854’s programmable 4

×–20×

REFCLK multiplier circuit generates the 300 MHz clock inter-

nally from a lower frequency external reference clock. This saves

the user the expense and difﬁculty of implementing a 300 MHz

clock source. Direct 300 MHz clocking is also accommodated

with either single-ended or differential inputs. Single-pin con-

ventional FSK and the enhanced spectral qualities of “ramped”

FSK are supported. The AD9854 uses advanced 0.35 micron

CMOS technology to provide this high level of functionality on

a single 3.3 V supply.

The AD9854 is available in a space-saving 80-lead LQFP

surface mount package and a thermally-enhanced 80-lead LQFP

package. The AD9854 is pin-for-pin compatible with the AD9852

single-tone synthesizer. It is speciﬁed to operate over the extended

industrial temperature range of –40

°C to +85°C.

OVERVIEW

The AD9854 quadrature output digital synthesizer is a highly

flexible device that will address a wide range of applications.

The device consists of an NCO with 48-bit phase accumulator,

programmable reference clock multiplier, inverse sinc ﬁlters,

digital multipliers, two 12-bit/300 MHz DACs, high-speed

analog comparator, and interface logic. This highly integrated

device can be conﬁgured to serve as a synthesized LO, agile clock

generator, and FSK/BPSK modulator. The theory of operation of

the functional blocks of the device, and a technical description

of the signal flow through a DDS device, can be found in a

tutorial from Analog Devices called “A Technical Tutorial on

Digital Signal Synthesis.” This tutorial is available on CD-ROM

and information on obtaining it can be found at the Analog

Devices DDS website at www.analog.com/dds. The tutorial

also provides basic applications information for a variety of

digital synthesis implementations. The DDS background subject

matter is not covered in this data sheet; the functions and features

of the AD9854 will be individually discussed herein.

USING THE AD9854

Internal and External Update Clock

This function is comprised of a bidirectional I/O pin, Pin 20, and a

programmable 32-bit down-counter. In order for programming

changes to be transferred from the I/O Buffer registers to the active

core of the DDS, a clock signal (low to high edge) must be externally

supplied to Pin 20 or internally generated by the 32-bit Update Clock.

An externally generated Update Clock is internally synchronized

with the system clock to prevent partial transfer of program

This mode gives the user complete control of when updated

program information becomes effective. The default mode is set

for internal update clock (Int Update Clk control register bit is

logic high). To switch to external update clock mode, the Int

Update Clk register bit must be set to logic low. The internal

update mode generates automatic, periodic update pulses whose

time period is set by the user.

An internally generated Update Clock can be established by

programming the 32-bit Update Clock registers (address 16–19

hex) and setting the Int Update Clk (address 1F hex) control

operates at the system clock/2 (150 MHz maximum) and counts

down from a 32-bit binary value (programmed by the user).

When the count reaches 0, an automatic I/O Update of the DDS

output or functions is generated. The update clock is internally

and externally routed on Pin 20 to allow users to synchronize

programming of update information with the update clock rate.

The time period between update pulses is given as:

(N+1)

× (SYSTEM CLOCK PERIOD × 2)

where N is the 32-bit value programmed by the user. Allow-

able range of N is from 1 to (2

32 –1). The internally generated

update pulse output on Pin 20 has a ﬁxed high time of eight system

clock cycles.

Shaped On/Off Keying

Allows user to control the ramp-up and ramp-down time of an

“on/off” emission from the I and Q DACs. This function is

used in “burst transmissions” of digital data to reduce the adverse

spectral impact of short, abrupt bursts of data. Users must ﬁrst

enable the digital multipliers by setting the OSK EN bit (con-

trol register address 20 hex) to logic high in the control register.

Otherwise, if the OSK EN bit is set low, the digital multipliers

responsible for amplitude-control are bypassed and the I and Q

DAC outputs are set to full-scale amplitude. In addition to set-

ting the OSK EN bit, a second control bit, OSK INT (also at

address 20 hex), must be set to logic high. Logic high selects the

linear internal control of the output ramp-up or ramp-down

function. A logic low in the OSK INT bit switches control of

the digital multipliers to user programmable 12-bit registers

allowing users to dynamically shape the amplitude transition in

practically any fashion. These 12-bit registers, labeled “Output

Shape Key I and Output Shape Key Q” are located at addresses

21 through 24 hex in Table V. The maximum output amplitude

is a function of the RSET resistor and is not programmable when

OSK INT is enabled.

ABRUPT ON/OFF KEYING

SHAPED ON/OFF KEYING

Figure 31. Shaped On/Off Keying

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