AD9854SLASHPCB datasheet(25/44 Pages) AD

25 / 44 page

AD9854

–25–

REV. 0

used to set the rate-of-change of the 12-bit digital multipliers of

the I and Q DACs to perform an output shaping function.

Twenty-Bit Ramp Rate Clock—when selected, this down-

counter takes the system clock (300 MHz maximum) and divides

it by a 20-bit binary value (programmed by the user) to produce

a user-deﬁned clock. The clock outputs one pulse every time the

counter counts down to zero. This clock is used to set the rate-

of-frequency-change of the ramped FSK or FM Chirp modes.

Forty-Eight-Bit Delta Frequency Register—is used only in

the Chirp and ramped-FSK modes. This register is loaded with a

48-bit word that represents the frequency increment value of

Frequency Accumulator (ACCU 1) whose output will be added

to a frequency that is set in either F1 or F2 frequency registers.

This register is periodically incremented at a rate set by the

20-bit ramp rate clock (150 MHz maximum).

Forty-Eight-Bit Delta Frequency Register—is programmed

with a 48-bit Frequency Tuning Word that is input to the 48-bit

Phase Accumulator (ACCU 2) and determines the output fre-

quency of the DDS in the single-tone mode. When ramped-FSK

or Chirp are selected, this register is sent to a digital adder where

it is summed with the output of ACCU 1 before being input to

ACCU 2. Therefore, the signal sent to ACCU 2 may be either

static or changing at a rate of up to 150 million 48-bit frequency

tuning words per second.

Power-Down—Several individual stages, when not needed,

can be powered down to reduce power consumption via the

programming registers while still maintaining functionality of

desired stages. These stages are identiﬁed in the Register Layout

table, address 1D hex. Power-down is achieved by setting the

speciﬁed bits to logic high. A logic low indicates that the stages

are powered up.

Furthermore, and perhaps most signiﬁcantly, two intensely digital

stages, the Inverse Sinc ﬁlters and the Digital Multiplier stages,

can be bypassed to achieve signiﬁcant power reduction through

programming of the control registers in address 20 hex. Again,

logic high will cause the stage to be bypassed. Of particular

importance is the Inverse Sinc ﬁlter as this stage consumes a

signiﬁcant amount of power.

A full power-down occurs when all four PD Bits in control

consumption to approximately 10 mW (3 mA).

Master RESET—logic high active, must be held high for a

minimum of 10 system clock cycles. This causes the communi-

cations bus to be initialized and loads default values listed in the

Table V.

AD9854/PCB 数据表(PDF) 25 Page - Analog Devices

AD9854/PCB 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载