AD9854SLASHPCB datasheet(17/44 Pages) AD

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AD9854

–17–

REV. 0

000 (SINGLE TONE)

MODE

TW1

000 (DEFAULT)

Figure 35. Default State to User-Deﬁned Output Transition

Table III. Function Availability vs. Mode of Operation

Single-Pin

Phase

Amplitude

Inverse

Frequency

Automatic

Phase

FSK/BPSK

Shaped-

Offset or

Control or

SINC

Tuning

Frequency

Mode

Adjust 1

Adjust 2

or HOLD

Keying

Modulation

Filter

Word 1

Word 2

Sweep

Single-Tone

FSK

Ramped FSK

CHIRP

BPSK

Differential REFCLK Enable

A high level on this pin enables the differential clock Inputs,

REFCLOCK and REFCLOCKB (Pins 69 and 68 respec-

tively). The minimum differential signal amplitude required

is 800 mV p-p. The centerpoint or common-mode range of the

differential signal can range from 1.6 V to 1.9 V.

When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK

(Pin 69) is the only active clock input. This is referred to as

the single-ended mode. In this mode, Pin 68 (REFCLKB) should

be tied low or high, but not left floating.

Parallel/Serial Programming Mode

Setting Pin 70 high invokes parallel mode, whereas setting Pin

70 low will invoke the serial programming mode. Please refer to

the text describing the serial and parallel programming proto-

col contained in this data sheet for further information.

Two control bits located at address 20 hex in the Table V apply

only to the serial programming mode. LSB First when high,

dictates that serial data will be loaded starting with the LSB of

the word. When low (the default value), serial data is loaded

starting with the MSB of the word. SDO Active when high indi-

cates that the SDO pin, Pin 18, is dedicated as an output to read

back data from the AD9854 registers. When SDO Active is low

(default value), this indicates that the SDIO pin, Pin 19, acts as

a bidirectional serial data input and output pin and Pin 18 has

no function in the serial mode.

DESCRIPTION OF AD9854 MODES OF OPERATION

There are ﬁve programmable modes of operation of the AD9854.

Selecting a mode requires that three bits in the Control Register

(parallel address 1F hex) be programmed as follows in Table II.

Table II. Mode Selection Table

Mode 2

Mode 1

Mode 0

Result

SINGLE-TONE

FSK

RAMPED FSK

CHIRP

BPSK

In each mode, engaging certain functions may or may not be

permitted. Shown in Table III is a listing of some important

functions and their availability for each mode.

Single-Tone (Mode 000)

This is the default mode when master reset is asserted or when

it is user-programmed into the control register. The Phase

Accumulator, responsible for generating an output frequency, is

presented with a 48-bit value from Frequency Tuning Word 1

registers whose default values are zero. Default values from the

remaining applicable registers will further deﬁne the single-tone

output signal qualities.

The default values after a master reset, deﬁne a safe, “no output”

value resulting in an output signal of 0 Hertz, 0 phase. Upon

power-up and reset the output from both I and Q DACs will be

a dc value equal to the midscale output current. This is the

default mode amplitude setting of zero. Refer to the digital multi-

plier section for further explanation of the output amplitude

control. It will be necessary to program all or some of the 28

program registers to realize a user-deﬁned output signal.

Figure 35 graphically shows the transition from the default con-

dition (0 Hz) to a user deﬁned output frequency (F1).

As with all Analog Devices DDSs, the value of the frequency

tuning word is determined using the following equation:

FTW = (Desired Output Frequency

× 2N)/SYSCLK.

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