AD9854SLASHPCB datasheet(22/44 Pages) AD

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AD9854

–22–

REV. 0

Basic FM Chirp Programming Steps

1. Program a start frequency into Frequency Tuning Word 1

(parallel register addresses 4–9 hex) hereafter called FTW1.

2. Program the frequency step resolution into the 48-bit, twos

complement, Delta Frequency Word (parallel register addresses

10–15 hex).

3. Program the rate of change (time at each frequency) into the

20-bit Ramp Rate Clock (parallel register addresses 1A–C).

4. When programming is complete, an I/O update pulse at Pin

20 will engage the program commands.

The necessity for a twos complement Delta Frequency Word is

to deﬁne the direction in which the FM chirp will move. If the

48-bit delta frequency word is negative (MSB is high) then the

incremental frequency changes will be in a negative direction

from FTW1. If the 48-bit word is positive (MSB is low) then

the incremental frequency changes will be in a positive direction.

It is important to note that the FTW1 is only a starting point for

FM chirp. There is no built-in restraint requiring a return to

FTW1. Once the FM chirp has left FTW1 it is free to move

(under program control) within the Nyquist bandwidth (dc to

1/2 system clock). Instant return to FTW1 is easily achieved,

though, and this option is explained in the next few paragraphs.

Two control bits are available in the FM Chirp mode that will

allow practically instantaneous return to the beginning frequency,

FTW1, or to 0 Hz. First, CLR ACC1 bit, register address 1F

hex, will, if set high, clear the 48-bit frequency accumulator (ACC1)

output with a retriggerable one-shot pulse of one system clock

duration. The 48-bit Delta Frequency Word input to the accu-

mulator is unaffected by CLR ACC1 bit. If the CLR ACC1 bit

is left high, a one-shot pulse will be delivered to the Frequency

Accumulator (ACC1) on every rising edge of the I/O Update

Clock. The effect is to interrupt the current chirp, reset the

frequency back to FTW1, and continue the chirp at the previously

programmed rate and direction. Clearing the Frequency Accu-

mulator in the chirp mode is illustrated in Figure 45. Not shown

in the diagram is the I/O update signal, which is either user-

supplied or internally generated. A discussion of I/O Update is

presented elsewhere in this data sheet.

Next, CLR ACC2 control bit (register address 1F hex) is available to

clear both the frequency accumulator (ACC1) and the phase

accumulator (ACC2). When this bit is set high, the output of the

phase accumulator will result in 0 Hz output from the DDS. As

long as this bit is set high, the frequency and phase accumulators

will be cleared, resulting in 0 Hz output. To return to previous

DDS operation, CLR ACC2 must be set to logic low. This bit is

useful in generating pulsed FM.

I/O UPDATE

CLOCK

MODE

FTW1

DFW

000 (DEFAULT)

RAMP RATE

011 (CHIRP)

DELTA FREQUENCY WORD

CLR ACC1

Figure 45. Effect of CLR ACC1 in FM Chirp Mode

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