AD9854SLASHPCB datasheet(16/44 Pages) AD

16 / 44 page

AD9854

–16–

REV. 0

Table I. REFCLK Multiplier Control Register Values

Multiplier Value

Ref Mult 4

Ref Mult 3

Ref Mult 2

Ref Mult 1

Ref Mult 0

400100

500101

600110

700111

801000

901001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

CENTER 50MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10MHz/

SPAN 100MHz

IMAGES

FUNDAMENTAL OUTPUT POWER DECREASES

WITH INCREASING FREQUENCY

Figure 33. Normal SIN(x)/x DAC Output Power Envelope

Filter

CENTER 50MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10MHz/

SPAN 100MHz

FUNDAMENTAL OUTPUT POWER IS

"FLAT" FROM DC TO 1/2 FCLK

Figure 34. Inverse SIN(x)/x (Inverse SINC) Filter Engaged

Inverse SINC Function

This ﬁlter precompensates input data to both DACs for the

SIN(x)/x roll-off function to allow wide bandwidth signals (such

as QPSK) to be output from the DACs without appreciable

amplitude variations that will cause increased EVM (error vector

magnitude). The inverse SINC function may be bypassed to

signiﬁcantly reduce power consumption, especially at higher

clock speeds. When the Q DAC is conﬁgured as a “control”

DAC, the inverse SINC function does not apply.

Inverse SINC is engaged by default and is bypassed by bringing

the “Bypass Inv SINC” bit high in control register 20 (hex) in

Table V.

REFCLK Multiplier

This is a programmable PLL-based reference clock multiplier

that allows the user to select an integer clock multiplying value

over the range of 4

× to 20× by which the REFCLK input will be

multiplied. Use of this function allows users to input as little as

15 MHz to produce a 300 MHz internal system clock. Five bits

in control register 1E hex set the multiplier value as follows in

Table I.

The REFCLK Multiplier function can be bypassed to allow

direct clocking of the AD9854 from an external clock source.

The system clock for the AD9854 is either the output of the

REFCLK Multiplier (if it is engaged) or the REFCLK inputs.

REFCLK may be either a single-ended or differential input by

setting Pin 64, DIFF CLK ENABLE, low or high respectively.

PLL Range Bit

The PLL Range Bit selects the frequency range of the REFCLK

Multiplier PLL. For operation from 200 MHz to 300 MHz

(internal system clock rate) the PLL Range Bit should be set to

Logic 1. For operation below 200 MHz, the PLL Range Bit

should be set to Logic 0. The PLL Range Bit adjusts the PLL

loop parameters for optimized phase noise performance within

each range.

Pin 61, PLL FILTER

This pin provides the connection for the external zero compen-

sation network of the PLL loop ﬁlter. The zero compensation

network consists of a 1.3 k

Ω resistor in series with a 0.01 µF

capacitor. The other side of the network should be connected to

as close as possible to Pin 60, AVDD. For optimum phase noise

performance the clock multiplier can be bypassed by setting the

“Bypass PLL” bit in control register address 1E.

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