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CDCM7005 数据表(PDF) 30 Page - Texas Instruments

部件名 CDCM7005
功能描述  3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
PDF  45 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCM7005 数据表(HTML) 30 Page - Texas Instruments

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F0004-01
No
No
No
PLL
Out-of-Lock?
PLL-Lock
Output
Set?
3-State Charge-Pump
Reference Clock
Back?
64 PFD
Lock-Cycles
Yes
Yes
Yes
Charge-Pump is switched into 3-State.
P-divider and Yx output are at normal operation.
The Charge-Pump remains in 3-State
until the Reference Clock is back. The 1st
valid Reference Clock at the PFD releases
the Charge-Pump.
The PLL acquire 64 lock cycles to phase
align to the input clock.
Frequency Hold-Over Function works in
combination with the Analog Lock-Detect
function only!
Start
PLL is out-of-lock if the phase
difference of Reference Clock and
Feedback Clock at PFD are outside the
predefined Lock-Detect-Window or if a
frequency offset occurs.
PLL has to be in LOCK to start
HOLD-Function.
(The Analog Lock output is not reset by the first Out-of-
Lock event. It stays ‘High’ depending on the analog time
delay (output C-load). The time delay must be long enough
to assure proper HOLD function)
(The ‘PLL-Lock Output Set?’ enquiry can be bypassed by
setting the HOLDTR bit to [1] (Word 3, Bit 11)
CDCM7005
SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013
www.ti.com
If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin is
released, the charge pump is switched back in to normal operation with the next valid reference clock cycle at
PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and all
outputs Yx are at normal operation.
HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to 3-
State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock is
back. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop.
The dedicated looking sequence and a digital phase alignment enable a fast lock.
Figure 22. Frequency HOLD-Over Function
30
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links :CDCM7005



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