CDCM7005

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SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

Word 1

PIN AFFECTED

POWER UP

BIT

BIT NAME

DESCRIPTION/FUNCTION

CONDITION

BGA

QFN

0

C0

Register Selection

1

1

C1

Register Selection

0

2

OUTSEL0

Output (Yx)

For Output Y0A, Y0B:

1

F1, G1

46, 47

Signaling Selection LVPECL = enabled [1]; LVCMOS = enabled [0];

3

OUTSEL1

For Outputs Y1A, Y1B:

1

H2, H3

3, 4

LVPECL = enabled [1]; LVCMOS = enabled [0];

4

OUTSEL2

For Outputs Y2A, Y2B:

1

H4, H5

7, 8

LVPECL = enabled [1]; LVCMOS = enabled [0];

5

OUTSEL3

For Outputs Y3A, Y3B:

1

H6, H7

11, 12

LVPECL = enabled [1]; LVCMOS = enabled [0];

6

OUTSEL4

For Outputs Y4A, Y4B:

1

G8, F8

16,17

LVPECL = enabled [1]; LVCMOS = enabled [0];

7

OUT0A0

Output Y0 Mode

Output Y0A Mode Bit 0

0

F1

46

8

OUT0A1

Output Y0A Mode Bit 1

0

F1

46

9

OUT0B0

Output Y0B Mode Bit 0

0

G1

47

10

OUT0B1

Output Y0B Mode Bit 1

0

G1

47

11

OUT1A0

Output Y1 Mode

Output Y1A Mode Bit 0

0

H2

3

12

OUT1A1

Output Y1A Mode Bit 1

0

H2

3

13

OUT1B0

Output Y1B Mode Bit 0

0

H3

4

14

OUT1B1

Output Y1B Mode Bit 1

0

H3

4

15

OUT2A0

Output Y2 Mode

Output Y2A Mode Bit 0

0

H4

7

16

OUT2A1

Output Y2A Mode Bit 1

0

H4

7

17

OUT2B0

Output Y2B Mode Bit 0

0

H5

8

18

OUT2B1

Output Y2B Mode Bit 1

0

H5

8

19

OUT3A0

Output Y3 Mode

Output Y3A Mode Bit 0

0

H6

11

20

OUT3A1

Output Y3A Mode Bit 1

0

H6

11

21

OUT3B0

Output Y3B Mode Bit 0

0

H7

12

22

OUT3B1

Output Y3B Mode Bit 1

0

H7

12

23

OUT4A0

Output Y4 Mode

Output Y4A Mode Bit 0

0

G8

16

24

OUT4A1

Output Y4A Mode Bit 1

0

G8

16

25

OUT4B0

Output Y4B Mode Bit 0

0

F8

17

26

OUT4B1

Output Y4B Mode Bit 1

0

F8

17

27

SREF

Status Ref.

Displays the status of the reference clock at the

0

C8

23

STATUS_REF output [0]

Displays the selected clock (high for PRI_REF and

low for SEC_REF clock) at the STATUS_REF

output [1]

28

SXOIREF

Status VCXO or

Selects STATUS_VCXO [0]

0

D8, A8

22, 25

I_REF_CP

Selects I_REF_CP [1] which enable external

reference resistor used for charge pump current and

analog PLL lock detect output current.

29

ADLOCK

Analog or Digital

Selects Digital PLL_LOCK [0]

0

A8

25

Lock

Selects Analog PLL_LOCK [1]

30

90DIV4

90 degree shift div- 90 degree output phase shift in div-4 mode on [1];

0

Yx

Yx

4

31

90DIV8

90 degree shift div- 90 degree output phase shift in div-8 mode on [1];

0

Yx

Yx

8

(1)

The P 16-Div has to be selected to obtain the 90 degree phase shift. If bit 30 or bit 31 is set, the Div-by-16 mode is no longer available.

The outputs are switched in pairs. Only one bit can be set at a time. If both bits set to [1] at the same time, no 90 degree phase shift

mode is selected (equal to off-mode setting).

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