CDCM7005_13 datasheet(20/45 Pages) TI

20 / 45 page

CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

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Word 2

POWER UP

PIN AFFECTED

BIT

DESCRIPTION/FUNCTION

CONDITIO

NAME

BGA

QFN

CP_DIR

CP Direction

Determines in which direction CP current regulates (Reference

Clock leads to Feedback Clock – see Figure 23)

– positive CP output current [0];

– negative CP output current [1];

PRECP

Preset charge pump output voltage to VCC_CP/2, on [1], off [0]

CP0

CP Current

CP Current Setting Bit 0

CP1

CP Current Setting Bit 1

CP2

CP Current Setting Bit 2

CP3

CP Current Setting Bit 3

PFD0

PFD Pulse

PFD Pulse Width PFD Bit 0

Width

PFD1

PFD Pulse Width PFD Bit 1

FBMUX0

FB_MUX

Feedback MUX Select Bit 0

FBMUX1

Feedback MUX Select Bit 1

FBMUX2

Feedback MUX Select Bit 2

Y0MUX0

Y0_MUX

Output Y0x Select Bit 0

F1, G1

46, 47

Y0MUX1

Output Y0x Select Bit 1

F1, G1

46, 47

Y0MUX2

Output Y0x Select Bit 2

F1, G1

46, 47

Y1MUX0

Y1_MUX

Output Y1x Select Bit 0

H2, H3

3, 4

Y1MUX1

Output Y1x Select Bit 1

H2, H3

3, 4

Y1MUX2

Output Y1x Select Bit 2

H2, H3

3, 4

Y2MUX0

Y2_MUX

Output Y2x Select Bit 0

H4, H5

7, 8

Y2MUX1

Output Y2x Select Bit 1

H4, H5

7, 8

Y2MUX2

Output Y2x Select Bit 2

H4, H5

7, 8

Y3MUX0

Y3_MUX

Output Y3x Select Bit 0

H6, H7

11, 12

Y3MUX1

Output Y3x Select Bit 1

H6, H7

11, 12

Y3MUX2

Output Y3x Select Bit 2

H6, H7

11, 12

Y4MUX0

Y4_MUX

Output Y4x Select Bit 0

G8, F8

16, 17

Y4MUX1

Output Y4x Select Bit 1

G8, F8

16, 17

Y4MUX2

Output Y4x Select Bit 2

G8, F8

16, 17

Power Down mode on [0], off [1]

RESHOL

RESET or HOLD Pin definition: RESET [0] or HOLD [1]

RESET

Resets all dividers [0] - (equal to RESET pin function)

HOLD

3-state charge pump [0] - (equal to HOLD pin function)

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