CDCM7005_13 datasheet(23/45 Pages) TI

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CDCM7005

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SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

Output Mode Selection for LVCMOS and LVPECL Outputs: Y0A, Y0B, Y1A …Y4B (Word 1)(1)

OUTSELx

OUTxB1

OUTxB0

LVCMOS

OUTxA1

OUTxA0

LVCMOS

Default

[YxB]

[YxA]

LVCMOS

Active

3-state

Inverting

Low

OUTSELx

OUTxB1

OUTxB0

OUTxA1

OUTxA0

LVCMOS

Default

[YxA]

LVPECL

Active

3-state

(1)

If the differential LVPECL output e.g. Y0A:Y0B is selected (bit 2 of word 1), then only bit 7 of word 1 defines the output mode for

Y0A:Y0B. The settings of bit 8, bit 9, and bit 10 of word 1 are therefore not relevant to the Y0A:Y0B. This applies for the other LVPECL

outputs as well.

Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment (Word 0)(1)

DLYM2 / DLYN2

DLYM1 / DLYN1

DLYM0 / DLYN0

Phase Offset

Default

0 ps

Yes

±160 ps

±320 ps

±480 ps

±830 ps

±1130 ps

±1450 ps

±1750 ps

(1)

If Progr. Delay M is set, all Yx outputs are lagging to the reference clock according to the value set. If Progr. If Delay N is set; all Yx

outputs are leading to the reference clock according to the value set. Above are typical values at VCC = 3.3 V, Temp = 25°C, PECL-

output relate to Div4 mode.

PFD Pulse Width Delay (Word 2)

PFD1(1)

PFD0(1)

PFD Pulse Width(1) (2)

Default(1)

1.5 ns

Yes

3 ns

4.5 ns

6 ns

(1)

The PFD pulse width delay gets around the dead zone of the PFD transfer function and reduces phase noise and reference spurs.

(2)

Typical values at V = 3.3 VCC, Temp = 25°C .

Lock-Detect Window (Word 3)

LOCKW1

LOCKW0

Phase-Offset at PFD Input(1)

Default

3.5 ns

8.5 ns

Yes

18.5 ns

Frequency offset(2)

(1)

Typical Values at VCC = 3.3 V, Temp = 25°C.

(2)

The PLL is out-of-lock (PLL_LOCK set low) if a certain frequency offset between reference frequency and feedback frequency (VCXO)

at PFD input is detected. The minimum detectable frequency offset depends on the device setting and can be calculated:

(a) foffsetPDF = fPFD - 1/(1/fPFD + PWD)

(b) foffsetPFD = detectable frequency offset at PFD between the reference frequency (fREF) and feedback frequency (fFB)

(d) PWD = PFD Pulse Width Delay

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