CDCM7005_13 datasheet(7/45 Pages) TI

7 / 45 page

CDCM7005

www.ti.com

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load and operating free air temperature

PARAMETER

MIN

TYP

MAX

UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

fREF_IN

LVCMOS primary or secondary reference clock frequency(1) (2)

200

MHz

tr/ tf

Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC

dutyREF

Duty cycle of PRI_REF or SEC_REF at VCC/2

40%

60%

VCXO_IN, VCXO_IN REQUIREMENTS

fVCXO_IN

VCXO clock frequency(3)

2200

MHz

tr/ tf

Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz(4)

dutyVCXO

Duty cycle of VCXO clock

40%

60%

SPI/CONTROL REQUIREMENTS (see Figure 14)

fCTRL_CLK

CTRL_CLK frequency

MHz

tsu1

CTRL_DATA to CTRL_CLK setup time

th2

CTRL_DATA to CTRL_CLK hold time

CTRL_CLK high duration

CTRL_CLK low duration

tsu5

CTRL_LE to CTRL_CLK setup time

tsu6

CTRL_CLK to CTRL_LE setup time

CTRL_LE pulse width

tr/ tf

Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC

PD, RESET, HOLD, REF_SEL REQUIREMENTS

tr / tf

Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC

(1)

At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the

STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.

(2)

fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).

(3)

If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!

(4)

Use a square wave for lower frequencies (< 80 MHz).

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL

fVCXO = 245.76 MHz,

fREF_IN = 30.72 MHz,

ICC_LVPECL

PFD = 240 kHz, ICP = 2 mA, all outputs

210

260

are LVPECL and Div-by-8 (load, see

Supply current (ICC over frequency see

Figure 13)

Figure 1 through Figure 4)

fVCXO = 245.76 MHz,

fREF_IN = 30.72 MHz,

ICC_LVCMOS

120

150

PFD = 240 kHz, ICP = 2 mA, All outputs

are LVCMOS and Div-by-8 (load, 10 pF)

fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V,

ICCPD

Power-down current

VCC_CP = 3.6 V,

100

300

µA

VI = 0 V or VCC

VO = 0 V or VCC – 0.8 V

±40

µA

High-impedance state output current

IOZ

for Yx outputs

VO = 0 V or VCC

±100

µA

Voltage on I_REF_CP (external current

12 k

Ω to GND at pin D8 (BGA), pin 22

VI_REF_CP

1.21

path for accurate charge pump current)

(QFN)

VBB

Output reference voltage

VCC = 3 V – 3.6 V; IBB = –0.2 mA

VCC–1.3

Output capacitance for Yx

VCC = 3.3 V, VO = 0 V or VCC

Input capacitance at PRI_REF and

VI = 0 V or VCC, VI = 0 V or VCC

2.7

SEC_REF

Input capacitance at CTRL_LE,

VI = 0 V or VCC

CTRL_CLOCK, CTRL_DATA

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