CDCM7005_13 datasheet(8/45 Pages) TI

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CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

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DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVCMOS

Output frequency, see (1), (2), Figure 6,

Load = 5 pF to GND, 1 k

Ω to VCC, 1 kΩ

fclk

250

MHz

and Figure 7

to GND

VIK

LVCMOS input clamp voltage

VCC = 3 V, II = –18 mA

–1.2

LVCMOS input current for CTRL_LE,

VI = 0 V or VCC, VCC = 3.6 V

±5

µA

CTRL_CLK, CTRL_DATA

LVCMOS input current for PD, RESET,

IIH

HOLD, REF_SEL, PRI_REF,

VI = VCC, VCC = 3.6 V

µA

SEC_REF, (see (3))

LVCMOS input current for PD, RESET,

IIL

HOLD, REF_SEL, PRI_REF,

VI = 0 V, VCC = 3.6 V

–15

–35

µA

SEC_REF, (see (3))

VCC = min to max,

VCC–0.1

IOH = –100 μA

High-level output voltage for LVCMOS

VOH

outputs

VCC = 3 V, IOH = –6 mA

2.4

VCC = 3 V, IOH = –12 mA

VCC = min to max,

0.1

IOL = 100 μA

Low-level output voltage for LVCMOS

VOL

outputs

VCC = 3 V, IOL = 6 mA

0.5

VCC = 3 V, IOL = 12 mA

0.8

IOH

High-level output current

VCC = 3.3 V, VO = 1.65 V

–30

IOL

Low-level output current

VCC = 3.3 V, VO = 1.65 V

VREF_IN = VCC/2, Y = VCC/2,

tpho

Phase offset (REF_IN to Y output)(4)

1.8

see Figure 11, Load = 10 pF

tsk(p)

LVCMOS pulse skew, see Figure 10

Crosspoint to VCC/2 load, see Figure 12

150

tpd(LH)

Crosspoint to VCC/2,

Propagation delay from VCXO_IN to

Load = 10 pF, see Figure 12 (PLL

2.5

Yx, see Figure 10

tpd(HL)

bypass mode)

All outputs have the same divider ratio

LVCMOS single-ended output skew,

tsk(o)

see (5) and Figure 10

Outputs have different divider ratios

Duty cycle

LVCMOS

VCC/2 to VCC/2

49%

51%

20% to 80% of swing (load

tslew-rate

Output rise/fall slew rate

2.4

3.5

V/ns

see Figure 12)

LVPECL

fclk

Output frequency, see (6) and Figure 5

Load, see Figure 13

1500

MHz

LVPECL input current

VI = 0 V or VCC

±20

µA

VOH

LVPECL high-level output voltage

Load, See Figure 13

VCC–1.18

VCC–0.81

VOL

LVPECL low-level output voltage

Load, See Figure 13

VCC–2

VCC–1.55

|VOD|

Differential output voltage

See Figure 9 and load, see Figure 13

500

VREF_IN = VCC/2 to cross point of Y,

tpho

Phase offset (REF_IN to Y output)(5)

–200

100

see Figure 11

tpd(LH)

Propagation delay time, VCXO_IN to

Cross point-to-cross point, load

340

490

640

Yx, see Figure 10

see Figure 13

tpd(HL)

Cross point-to-cross point, load

tsk(p)

LVPECL pulse skew, see Figure 10

see Figure 13

(1)

fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA

package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4).

(2)

Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing may no longer meet the output specification.

(3)

These inputs have an internal 150-k

Ω pullup resistor.

(4)

This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M

and VCXO delay N).

(5)

The tsk(o) specification is only valid for equal loading of all outputs.

(6)

Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing may no longer meet the output specification.

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