CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

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FUNCTIONAL DESCRIPTION OF THE LOGIC

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

Div by

Default

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

2

0

0

0

0

0

0

0

0

1

0

3

0

0

0

0

0

0

0

0

1

1

4

•

•

•

0

0

0

1

1

1

1

1

1

1

128

Yes

•

•

•

1

1

1

1

1

1

1

1

0

1

1022

1

1

1

1

1

1

1

1

1

0

1023

1

1

1

1

1

1

1

1

1

1

1024

(4)

If the divider value is Q, then the code will be the binary value of (Q–1).

N11

N10

N0

N8

N7

N6

N5

N4

N3

N2

N1

N0

Div by

Default

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

1

2

0

0

0

0

0

0

0

0

0

0

1

0

3

0

0

0

0

0

0

0

0

0

0

1

1

4

•

•

•

0

0

0

0

0

1

1

1

1

1

1

1

128

Yes

•

•

•

1

1

1

1

1

1

1

1

1

1

0

1

4094

1

1

1

1

1

1

1

1

1

1

1

0

4095

1

1

1

1

1

1

1

1

1

1

1

1

4096

(1)

If the divider value is Q, then the code will be the binary value of (Q–1).

(2)

The frequency applied to the Divider N must be smaller than 300 MHz. A sufficient P Divider must be selected with the FB_MUX to

maintain this criteria.

22

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