CDCM7005_13 datasheet(4/45 Pages) TI

4 / 45 page

CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

www.ti.com

Table 1. PIN ASSINGMENT

TERMINAL

I/O

DESCRIPTION

NAME

BGA

QFN

D7, E3,

2, 5, 6,

E4, E5,

9, 10,

E6, E7,

13, 15,

3.3-V supply. VCC and AVCC should always have the same supply voltage. It is

VCC

E8, F7,

18, 19,

Power

recommended that AVCC use its own supply filter.

G2, G3,

20, 21,

G4, G5,

41, 44,

G6, G7

45; 48

B2, B3,

B4, B5,

B6, B7,

B8, C2,

Thermal

D2, D3,

GND

pad and

Ground

D4, D5,

pin 24

D6, E2,

F2, F3,

F4, F5,

C3, C4,

27, 30,

Analog

3.3-V analog power supply. There is no internal connection between AVCC and

AVCC

C5, C6,

32, 38,

Power

VCC. It is recommended that AVCC use its own supply filter.

This is the charge pump power supply pin used to have the same supply as the

VCC_CP

Power

external VCO. It can be set from 2.3 V to 3.6 V.

LVCMOS input, control latch enable for serial programmable Interface (SPI), with

CTRL_LE

hysteresis. Unused or floating inputs must be tied to proper logic level. A 20k

Ω or

larger pull

−up resistor to VCC is recommended.

LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or

CTRL_CLK

floating inputs must be tied to proper logic level. A 20k

Ω or larger pull−up resistor

to VCC is recommended.

LVCMOS input, serial control data input for SPI, with hysteresis. Unused or

CTRL_DATA

floating inputs must be tied to proper logic level. A 20k

Ω or larger pull−up resistor

to VCC is recommended.

LVCMOS input, asynchronous power down (PD) signal. This pin is low active and

can be activated external or by the corresponding bit in the SPI register (in case of

logic high, the SPI setting is valid). Switches the device into power-down mode.

Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or

PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin

and all Yx outputs. Sets the SPI register to default value; has internal 150-k

Ω

pullup resistor. It is recommended to ramp up the PD with the same time as VCC

and AVCC or later. The ramp up rate of the PD should not be faster than the ramp

up rate of VCC and AVCC.

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET

is the default function. This pin is low active and can be activated external or via

the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)

is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider

settings are maintained in SPI registers). The LVPECL outputs are static low and

high respectively and the LVCMOS outputs are all low or high if inverted. RESET

RESET or

is not edge triggered and should have a pulse duration of at least 5 ns.

HOLD

In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is

released and with the next valid reference clock cycle the charge pump is

switched back in to normal operation (CP stays in 3-state as long as no reference

clock is valid). During HOLD, the P divider and all outputs Yx are at normal

operation. This mode allows an external control of the frequency hold-over mode.

The input has an internal 150-k

Ω pullup resistor.

VCXO_IN

VCXO LVPECL input

VCXO_IN

Complementary VCXO LVPECL input

LVCMOS input for the primary reference clock, with an internal 150-k

Ω pullup

PRI_REF

resistor and input hysteresis.

LVCMOS input for the secondary reference clock, with an internal 150-k

Ω pullup

SEC_REF

resistor and input hysteresis.

Submit Documentation Feedback

Product Folder Links :CDCM7005

CDCM7005 数据表(PDF) 4 Page - Texas Instruments

CDCM7005 数据表(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载

链接网址

CDCM7005 数据表(PDF) 4 Page - Texas Instruments

CDCM7005 数据表(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表 下载

链接网址

数据表下载