AD822 datasheet(47/88 Pages) AD

47 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 47 of 88

Using the SPI Interface

Depending on the configuration of the bits in the SPICON SFR

shown in Table 18, the ADuC841/ADuC842/ADuC843 SPI

interface transmits or receives data in a number of possible

modes. Figure 54 shows all possible SPI configurations for the

parts, and the timing relationships and synchronization

between the signals involved. Also shown in this figure is the

SPI interrupt bit (ISPI) and how it is triggered at the end of each

byte-wide communication.

SCLOCK

(CPOL = 1)

SCLOCK

(CPOL = 0)

(CPHA = 1)

(CPHA = 0)

SAMPLE INPUT

ISPI FLAG

DATA OUTPUT

ISPI FLAG

SAMPLE INPUT

DATA OUTPUT

MSB BIT 6 BIT 5

BIT 4 BIT 3 BIT 2 BIT 1 LSB

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

Figure 54. SPI Timing, All Modes

SPI Interface—Master Mode

In master mode, the SCLOCK pin is always an output and

generates a burst of eight clocks whenever user code writes to

the SPIDAT register. The SCLOCK bit rate is determined by

SPR0 and SPR1 in SPICON. Also note that the SS pin is not

used in master mode. If the parts need to assert the SS pin on an

external slave device, a port digital output pin should be used.

In master mode, a byte transmission or reception is initiated by

a write to SPIDAT. Eight clock periods are generated via the

SCLOCK pin and the SPIDAT byte being transmitted via MOSI.

With each SCLOCK period, a data bit is also sampled via MISO.

After eight clocks, the transmitted byte will be completely

transmitted, and the input byte will be waiting in the input shift

will occur if enabled. The value in the shift register will be

latched into SPIDAT.

SPI Interface—Slave Mode

In slave mode, SCLOCK is an input. The SS pin must also be

driven low externally during the byte communication. Trans-

mission is also initiated by a write to SPIDAT. In slave mode, a

data bit is transmitted via MISO, and a data bit is received via

MOSI through each input SCLOCK period. After eight clocks,

the transmitted byte will be completely transmitted, and the

input byte will be waiting in the input shift register. The ISPI

flag will be set automatically, and an interrupt will occur if

enabled. The value in the shift register will be latched into

SPIDAT only when the transmission/reception of a byte has

been completed. The end of transmission occurs after the

eighth clock has been received if CPHA = 1, or when SS returns

high if CPHA = 0.

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