AD822 datasheet(75/88 Pages) AD

75 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 75 of 88

5 V Part

For DVDD below 4.5 V, the internal POR holds the part in reset.

As DVDD rises above 4.5 V, an internal timer times out for

approximately 128 ms before the part is released from reset. The

user must ensure that the power supply has reached a stable

4.75 V minimum level by this time. Likewise on power-down,

the internal POR holds the part in reset until the power supply

has dropped below 1 V. Figure 83 illustrates the operation of the

internal POR in detail.

128ms

1.0V

128ms

4.75V

1.0V TYP

INTERNAL

CORE RESET

DVDD

Figure 83. Internal POR Operation

Grounding and Board Layout Recommendations

As with all high resolution data converters, special attention

must be paid to grounding and PC board layout of ADuC841/

ADuC842/ADuC843 based designs to achieve optimum

performance from the ADC and the DACs. Although the parts

have separate pins for analog and digital ground (AGND and

DGND), the user must not tie these to two separate ground

planes unless the two ground planes are connected together

very close to the part, as illustrated in the simplified example of

Figure 84a. In systems where digital and analog ground planes

are connected together somewhere else (for example, at the

system’s power supply), they cannot be connected again near the

part since a ground loop would result. In these cases, tie all the

part’s AGND and DGND pins to the analog ground plane, as

illustrated in Figure 84b. In systems with only one ground plane,

ensure that the digital and analog components are physically

separated onto separate halves of the board such that digital

return currents do not flow near analog circuitry and vice versa.

The part can then be placed between the digital and analog

sections, as illustrated in Figure 84c.

In all of these scenarios, and in more complicated real-life

applications, keep in mind the flow of current from the supplies

and back to ground. Make sure the return paths for all currents

are as close as possible to the paths that the currents took to

reach their destinations. For example, do not power components

on the analog side of Figure 84b with DVDD since that would

force return currents from DVDD to flow through AGND. Also,

try to avoid digital currents flowing under analog circuitry,

which could happen if the user places a noisy digital chip on the

left half of the board in Figure 84c. Whenever possible, avoid

large discontinuities in the ground plane(s) (like those formed

by a long trace on the same layer), since they force return

signals to travel a longer path. And of course, make all connec-

tions to the ground plane directly, with little or no trace

separating the pin from its via to ground.

If the user plans to connect fast logic signals (rise/fall time <

5 ns) to any of the part’s digital inputs, a series resistor should be

added to each relevant line to keep rise and fall times longer

than 5 ns at the part’s input pins. A value of 100 Ω or 200 Ω is

usually sufficient to prevent high speed signals from coupling

capacitively into the part and from affecting the accuracy of

ADC conversions.

DGND

AGND

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

GND

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

DGND

AGND

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS

HERE

Figure 84. System Grounding Schemes

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