AD822 datasheet(53/88 Pages) AD

53 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 53 of 88

WATCHDOG TIMER

The purpose of the watchdog timer is to generate a device reset

or interrupt within a reasonable amount of time if the ADuC841/

ADuC842/ADuC843 enter an erroneous state, possibly due to a

programming error or electrical noise. The watchdog function

can be disabled by clearing the WDE (watchdog enable) bit in

the watchdog control (WDCON) SFR. When enabled, the

watchdog circuit generates a system reset or interrupt (WDS) if

the user program fails to set the watchdog (WDE) bit within a

predetermined amount of time (see PRE3-0 bits in Table 23.

The watchdog timer is clocked directly from the 32 kHz

external crystal on the ADuC842/ADuC843. On the ADuC841,

the watchdog timer is clocked by an internal R/C oscillator at

32 kHz ±10%. The WDCON SFR can be written only by user

software if the double write sequence described in WDWR

below is initiated on every write access to the WDCON SFR.

WDCON Watchdog Timer

Control Register

SFR Address

C0H

Power-On Default

10H

Bit Addressable

Yes

Table 23. WDCON SFR Bit Designations

Bit No.

Name

Description

PRE3

Watchdog Timer Prescale Bits.

PRE2

The watchdog timeout period is given by the equation

tWD = (2PRE × (29/ fXTAL))

PRE1

(0 – PRE – 7; fXTAL = 32.768 kHz (ADuC842/ADuC843), or 32kHz ± 10%(ADuC841) )

PRE3

PRE2

PRE1

PRE0

Timeout Period (ms)

Action

15.6

Reset or Interrupt

31.2

Reset or Interrupt

62.5

Reset or Interrupt

125

Reset or Interrupt

250

Reset or Interrupt

500

Reset or Interrupt

1000

Reset or Interrupt

2000

Reset or Interrupt

0.0

Immediate Reset

PRE0

PRE3–0 > 1000

Reserved

WDIR

Watchdog Interrupt Response Enable Bit.

If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the

watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction, and it is also a fixed,

high priority interrupt. If the watchdog is not being used to monitor the system, it can be used alternatively as a

timer. The prescaler is used to set the timeout period in which an interrupt will be generated.

WDS

Watchdog Status Bit.

Set by the watchdog controller to indicate that a watchdog timeout has occurred.

Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.

WDE

Watchdog Enable Bit.

Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog

timeout period, the watchdog generates a reset or interrupt, depending on WDIR.

Cleared under the following conditions: user writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt.

Watchdog Write Enable Bit.

To write data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very

next instruction must be a write instruction to the WDCON SFR.

For example:

CLR

;disable interrupts while writing

;to WDT

SETB

WDWR

;allow write to WDCON

MOV

WDCON,#72H

;enable WDT for 2.0s timeout

WDWR

SETB

;enable interrupts again (if rqd)

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