AD822 datasheet(64/88 Pages) AD

64 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 64 of 88

TIMER/COUNTER OPERATING MODES

The following sections describe the operating modes for

Timer/Counter 2. The operating modes are selected by bits in

the T2CON SFR, as shown in Table 31.

Table 31. T2CON Operating Modes

RCLK (or) TCLK

CAP2

TR2

Mode

16-Bit Autoreload

16-Bit Capture

Baud Rate

OFF

16-Bit Autoreload Mode

Autoreload mode has two options that are selected by Bit EXEN2

in T2CON. If EXEN2 = 0, then when Timer 2 rolls over, it not

only sets TF2 but also causes the Timer 2 registers to be

reloaded with the 16-bit value in registers RCAP2L and RCAP2H,

which are preset by software. If EXEN2 = 1, then Timer 2 still

performs the above, but with the added feature that a 1-to-0

transition at external input T2EX will also trigger the 16-bit

reload and set EXF2. Autoreload mode is illustrated in Figure 70.

16-Bit Capture Mode

Capture mode also has two options that are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer

or counter that, upon overflowing, sets Bit TF2, the Timer 2

overflow bit, which can be used to generate an interrupt. If

EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0

transition on external input T2EX causes the current value in

the Timer 2 registers, TL2 and TH2, to be captured into

registers RCAP2L and RCAP2H, respectively. In addition, the

transition at T2EX causes Bit EXF2 in T2CON to be set, and

EXF2, like TF2, can generate an interrupt. Capture mode is

illustrated in Figure 71. The baud rate generator mode is

selected by RCLK = 1 and/or TCLK = 1.

In either case, if Timer 2 is being used to generate the baud rate,

the TF2 interrupt flag will not occur. Therefore, Timer 2

interrupts will not occur, so they do not have to be disabled. In

this mode, the EXF2 flag, however, can still cause interrupts,

which can be used as a third external interrupt. Baud rate

generation is described as part of the UART serial port

operation in the following section.

CORE

CLK*

C/T2 = 0

C/T2 = 1

TR2

CONTROL

TL2

(8 BITS)

TH2

(8 BITS)

RELOAD

TF2

EXF2

TIMER

INTERRUPT

EXEN2

CONTROL

TRANSITION

DETECTOR

T2EX

RCAP2L

RCAP2H

* CORE CLK IS DEFINED BY THE CD BITS IN PLLCON

Figure 70. Timer/Counter 2, 16-Bit Autoreload Mode

TF2

CORE

CLK

TR2

CONTROL

TL2

(8 BITS)

TH2

(8 BITS)

CAPTURE

EXF2

TIMER

INTERRUPT

EXEN2

CONTROL

TRANSITION

DETECTOR

T2EX

RCAP2L

RCAP2H

C/ T2 = 0

C/ T2 = 1

* CORE CLK IS DEFINED BY THE CD BITS IN PLLCON

Figure 71. Timer/Counter 2, 16-Bit Capture Mode

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