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AD822 数据表(PDF) 48 Page - Analog Devices |
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AD822 数据表(HTML) 48 Page - Analog Devices |
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48 / 88 page  ADuC841/ADuC842/ADuC843 Rev. 0 | Page 48 of 88 I2C COMPATIBLE INTERFACE The ADuC841/ADuC842/ADuC843 support a fully licensed I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin, and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. To enable the I2C interface, the SPI interface must be turned off (see SPE in Table 18) or the SPI interface must be moved to P3.3, P3.4, and P3.5 via the CFG841.1/CFG842.1 bit. Application Note uC001 describes the operation of this interface as imple- mented and is available from the MicroConverter website at www.analog.com/microconverter. Three SFRs are used to control the I2C interface and are described in the following tables. I2CCON I2C Control Register SFR Address E8H Power-On Default 00H Bit Addressable Yes Table 19. I2CCON SFR Bit Designations, Master Mode Bit No. Name Description 7 MDO I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on the SDATA pin if the data output enable (MDE) bit is set. 6 MDE I2C Software Master Data Output Enable Bit (Master Mode Only). Set by the user to enable the SDATA pin as an output (Tx). Cleared by the user to enable the SDATA pin as an input (Rx). 5 MCO I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on the SCLOCK pin. 4 MDI I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0. 3 I2CM I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by the user to enable I2C hardware slave mode. 2 ---- Reserved. 1 ---- Reserved. 0 ---- Reserved. Table 20. I2CCON SFR Bit Designations, Slave Mode Bit No. Name Description 7 I2CSI I2C Stop Interrupt Enable Bit. Set by the user to enable I2C stop interrupts. If set, a stop bit that follows a valid start condition generates an interrupt. Cleared by the user to disable I2C stop interrupts. 6 I2CGC I2C General Call Status Bit. Set by hardware after receiving a general call address. Cleared by the user. 5 I2CID1 I2C Interrupt Decode Bits. 4 I2CID0 Set by hardware to indicate the source of an I2C interrupt. 00 Start and Matching Address. 01 Repeated Start and Matching Address. 10 User Data. 11 Stop after a Start and Matching Address. 3 I2CM I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by the user to enable I2C hardware slave mode. |
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