AD822 datasheet(26/88 Pages) AD

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ADuC841/ADuC842/ADuC843

Rev. 0 | Page 26 of 88

ADCCON3—(ADC Control SFR 3)

The ADCCON3 register controls the operation of various

calibration modes and also indicates the ADC busy status.

SFR Address

F5H

SFR Power-On Default

00H

Bit Addressable

Table 9. ADCCON3 SFR Bit Designations

Bit No.

Name

Description

BUSY

ADC Busy Status Bit.

A read-only status bit that is set during a valid ADC conversion or during a calibration cycle.

Busy is automatically cleared by the core at the end of conversion or calibration.

RSVD

Reserved. This bit should always be written as 0.

AVGS1

Number of Average Selection Bits.

This bit selects the number of ADC readings that are averaged during a calibration cycle.

AVGS0

AVGS1

AVGS0

Number of Averages

RSVD

Reserved. This bit should always be written as 0.

RSVD

This bit should always be written as 1 by the user when performing calibration.

TYPICAL

Calibration Type Select Bit.

This bit selects between offset (zero-scale) and gain (full-scale) calibration.

Set to 0 for offset calibration.

Set to 1 for gain calibration.

SCAL

Start Calibration Cycle Bit.

When set, this bit starts the selected calibration cycle.

It is automatically cleared when the calibration cycle is completed.

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