AD822 datasheet(19/88 Pages) AD

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ADuC841/ADuC842/ADuC843

Rev. 0 | Page 19 of 88

MEMORY ORGANIZATION

The ADuC841/ADuC842/ADuC843 each contain four different

memory blocks:

•

Up to 62 kBytes of on-chip Flash/EE program memory

•

4 kBytes of on-chip Flash/EE data memory

•

256 bytes of general-purpose RAM

•

2 kBytes of internal XRAM

Flash/EE Program Memory

The parts provide up to 62 kBytes of Flash/EE program mem-

ory to run user code. The user can run code from this internal

memory only. Unlike the ADuC812, where code execution can

overflow from the internal code space to external code space

once the PC becomes greater than 1FFFH, the parts do not

support the roll-over from F7FFH in internal code space to

F800H in external code space. Instead, the 2048 bytes between

F800H and FFFFH appear as NOP instructions to user code.

This internal code space can be downloaded via the UART

serial port while the device is in-circuit. 56 kBytes of the

program memory can be reprogrammed during run time; thus

the code space can be upgraded in the field by using a user

defined protocol, or it can be used as a data memory. This is

discussed in more detail in the Flash/EE Memory section.

For the 32 kBytes memory model, the top 8 kBytes function as

the ULOAD space; this is explained in the Flash/EE Memory

section.

Flash/EE Data Memory

4 kBytes of Flash/EE data memory are available to the user and

can be accessed indirectly via a group of control registers

mapped into the special function register (SFR) area. Access to

the Flash/EE data memory is discussed in detail in the Flash/EE

Memory section.

General-Purpose RAM

The general-purpose RAM is divided into two separate

memories: the upper and the lower 128 bytes of RAM. The

lower 128 bytes of RAM can be accessed through direct or

indirect addressing. The upper 128 bytes of RAM can be

accessed only through indirect addressing because it shares the

same address space as the SFR space, which can be accessed

only through direct addressing.

The lower 128 bytes of internal data memory are mapped as

shown in Figure 23. The lowest 32 bytes are grouped into four

banks of eight registers addressed as R0 to R7. The next 16 bytes

(128 bits), locations 20H to 2FH above the register banks, form

a block of directly addressable bit locations at Bit Addresses

00H to 7FH. The stack can be located anywhere in the internal

memory address space, and the stack depth can be expanded up

to 2048 bytes.

Reset initializes the stack pointer to location 07H and incre-

ments it once before loading the stack to start from location

08H, which is also the first register (R0) of register bank 1. Thus,

if the user needs to use more than one register bank, the stack

pointer should be initialized to an area of RAM not used for

data storage.

07H

0FH

17H

1FH

2FH

7FH

00H

08H

10H

18H

20H

RESET VALUE OF

STACK POINTER

30H

FOUR BANKS OF EIGHT

REGISTERS

R0 TO R7

BIT-ADDRESSABLE

(BIT ADDRESSES)

GENERAL-PURPOSE

AREA

BANKS

SELECTED

VIA

BITS IN PSW

Figure 23. Lower 128 Bytes of Internal Data Memory

The parts contain 2048 bytes of internal XRAM, 1792 bytes of

which can be configured to an extended 11-bit stack pointer.

By default, the stack operates exactly like an 8052 in that it rolls

over from FFH to 00H in the general-purpose RAM. On the

parts, however, it is possible (by setting CFG841.7 or CFG842.7)

to enable the 11-bit extended stack pointer. In this case, the

stack rolls over from FFH in RAM to 0100H in XRAM.

The 11-bit stack pointer is visible in the SP and SPH SFRs. The

SP SFR is located at 81H as with a standard 8052. The SPH SFR

is located at B7H. The 3 LSBs of this SFR contain the 3 extra bits

necessary to extend the 8-bit stack pointer into an 11-bit stack

pointer.

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