ST802RT1AFR datasheet(15/58 Pages) STMICROELECTRONICS

15 / 58 page

ST802RT1A, ST802RT1B

Pin description

Doc ID 17049 Rev 1

15/58

Pin n°

Name

Type

Description

3, 16,

19, 20,

GNDA

Ground Analog ground

Strap pins

The ST802RT1x uses many of the functional pins as strap options. The values of these pins are sampled during

reset hardware or power-up and used to strap the device into specific modes of operation.

The ST802RT1x provides simple strap options to automatically configure some device modes with no device

register configuration necessary. All strap pins have a weak internal pull-up or pull-down. If the default strap value is

needed to be changed, they should not be connected directly to VCC or GND and an external 2.2 kΩ resistor should

be used.

The software reset and the power down through the PD pin cannot be used to change the strap configuration

LPBK_EN

S, PD

Loop-back enable

MII_CFG0

MII_CFG1

S, PD

MII Mode Select: This strapping option pair determines the operating mode of

the MAC Data Interface. Default operation (No pull-ups) enables normal MII

mode of operation. Strapping mii_cfg0 high causes the device to be in RMII

mode of operation, determined by the status of the mii_cfg1 strap. Since the

pins include internal pull-downs, the default values are 0.

See Table 6 for details and configurations

AN_EN

AN_0

AN_1

S, PU

Auto-negotiation enable: When high, this enables auto-negotiation with the

capability set by the an_0 and an_1 pins. When low, this puts the part into

Forced Mode with the capability set by the an_0 and an_1 pins.

an_0 / an_1: These input pins control the forced or advertised operating mode

of the ST802RT1x according to Table 7. The value on these pins is set by

connecting the input pins to GND (0) or VCC (1) through 2.2 k

Ω resistors.

These pins should NEVER be connected directly to GND or VCC.

The value set at this input is latched into the ST802RT1x at Hardware-Reset.

The float/pull-down statuses of these pins are latched into the basic mode

control register and the auto-negotiation advertisement register during

hardware-reset.

The default is 111 since these pins have internal pull-up (see Table 7).

PHYADDR0

PHYADDR1

PHYADDR2

PHYADDR3

PHYADDR4

S, PU

S, PD

PHY address [4:0]. These pins are used to provide the address which is latched

into the internal receive mode control register RN14 (0x14h) after the reset.

PHYADDR0 pin has weak internal pull-up resistor.

PHYADDR[4:1] pins have weak internal pull-down resistors.

An external 2.2 k

Ω resistor should be used for pull-up/down the pins

Table 4.

Pin functions of the ST802RT1x (continued)

ST802RT1AFR 数据表(PDF) 15 Page - STMicroelectronics

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ST802RT1AFR 数据表(PDF) 15 Page - STMicroelectronics

ST802RT1AFR 数据表(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

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