ST802RT1AFR datasheet(44/58 Pages) STMICROELECTRONICS

44 / 58 page

Device operation

ST802RT1A, ST802RT1B

44/58

Doc ID 17049 Rev 1

7.15

Transmit isolation

Transmit isolation isolates the PHY from the MII and Tx +/- interface and is activated by

setting bit 5 of the 100Base-TX control register (RN13[5]). As with isolate mode, all MII

inputs are ignored and all MII outputs are tri-stated. Additionally, all link pulses are

suppressed.

7.16

Automatic MDI / MDIX feature

The automatic MDI / MDIX feature compensates for using an external crossover cable. With

auto-MDIX, the ST802RT1x automatically detects what the other device is and switches the

TX & RX pins accordingly. The state machine basically controls the switching of the tdp/tdn

and the rdp/rdn signals prior to the auto-negotiation communication. The swapping occurs

to allow FLP/NLP to be transmitted and received in the event that the external cable

connections have been swapped.

7.17

RMII interface

The reduced media independent interface (RMII) provides a low-cost alternative to the IEEE

802.3u MII interface. It can support 10 and 100 Mbit data rates with a single clock, using

independent 2-bit wide transmit and receive paths. A single synchronous reference clock

(SCLK pin 32) of 50 MHz is used as a timing reference for all transmitters and receivers. By

doubling the clock frequency relative to the MII, four pins are saved in the data path, which

uses two transmit data inputs and two receive data outputs instead of four lines for each

direction in the MII interface. Since start-of-packet and end-of-packet timing information is

preserved across the interface, the MAC is able to derive the COL signal from the receive

and transmit data delimiters, saving another pin.

Figure 7.

Transmit isolation

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