ST802RT1AFR datasheet(19/58 Pages) STMICROELECTRONICS

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ST802RT1A, ST802RT1B

Registers and descriptors description

Doc ID 17049 Rev 1

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Soft reset: In order to reset the ST802RT1x by software control, a “1” must be written to bit

15 of the control register using a serial management interface write operation. The bit clears

itself after the reset process is complete, and does not need to be cleared using a second

MII write. Writes to other control register bits have no effect until the reset process is

completed, which requires approximately 1 millisecond. Writing a “0” to this bit has no effect.

Since this bit is self-clearing, after a few cycles from a write operation, it returns a “0” when

read.

Local loop-back: The ST802RT1x may be placed into loop-back mode by writing a “1” to

bit 14 of the control register. The loop-back mode may be cleared by writing a “0” to bit 14 of

the control register, or by resetting the chip. When this bit is read, it returns a “1” when the

chip is in software-controlled loop-back mode; otherwise it returns a “0”.

Speed selection: If auto-negotiation is enabled, this bit has no effect on the speed

selection. However, if auto-negotiation is disabled by software control, the operating speed

of the ST802RT1x can be forced by writing the appropriate value to bit 13 of the control

10BASE-T operation. When this bit is read, it returns the value of the software-controlled

forced speed selection only.

Auto-negotiation enable: Auto-negotiation can be disabled by one of two methods:

hardware or software control. If the AN_EN input pin is driven to “0”, auto-negotiation is

disabled by hardware control. If bit 12 of the control register is written with a value of “0”,

auto-negotiation is disabled by software control. When auto-negotiation is disabled in this

manner, writing a “1” to the same bit of the control register re-enables auto-negotiation. If

auto-negotiation is disabled in this manner and the chip is reset the auto-negotiation follows

the strap configuration. Writing to this bit has no effect when auto-negotiation has been

disabled by hardware control. When read, this bit returns the value most recently written to

this location, or “1” if it has not been written since the last chip reset.

Power-down: If set to '1', the channel is powered down. If this bit is set for all channels, then

the IO pad directions are forced and the device is in power-down state. Refer to Section 7.9

for a more detailed explanation of the power-down operation.

Isolate: The PHY may be isolated from its media independent interface (MII) by writing a

“1” to bit 10 of the control register. All MII outputs are tri-stated, except tx_clk, and all MII

inputs are ignored. Since the MII management interface is still active, the isolate mode may

Bit

Bit name

Description

Default

type

Type

Collision test

1 -> Collision test enabled

0 -> Normal operation

Active only in loop-back mode (RN00[14]=1)

0RW

RESERVED

Not used

RESERVED

Not used

RESERVED

Not used

RESERVED

Not used

RESERVED

Not used

RESERVED

Not used

RESERVED

Not used

Table 10.

RN00 [0d00, 0x00]: Control register (continued)

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