ST802RT1AFR datasheet(39/58 Pages) STMICROELECTRONICS

39 / 58 page

ST802RT1A, ST802RT1B

Device operation

Doc ID 17049 Rev 1

39/58

Wave-shaper and media signal driver: In order to reduce the energy of the harmonic

frequency of transmission signals, the device provides the wave-shaper prior to the line

driver to smooth out, but maintain symmetric, the rising/falling edge of the transmission

signals. The wave-shaped signals include the 100Base-TX and 10Base-T, and both are

passed to the same media signal driver.

7.2

100Base-TX receive operation

In the 100Base-TX receiving operation, the device provides the receiving functions of the

PMD, PMA, and PCS for receiving incoming data signals through a category 5 UTP cable

and an isolation transformer with a 1.414:1 turn ratio. It includes the adaptive equalizer and

baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ and serial-to-parallel, the

PLL for clock and data recovery, the de-scrambler, and the decoder for 5B/4B.

Adaptive equalizer and baseline wander: the high speed signals over the unshielded (or

shielded) twisted pair cable induces amplitude attenuation and phase shifting. Furthermore,

these effects depend on the signal frequency, cable type, cable length and the connectors of

the cabling. So a reliable adaptive equalizer and baseline wander to compensate for all the

amplitude attenuation and phase shifting are necessary. The transceiver provides robust

circuits to perform these functions.

MLT3 to NRZI decoder and PLL for data recovery: after receiving the proper MLT3 signals,

the device converts the MLT3 to NRZI code for further processing. The compensated NRZI

signals at 125 MHz are then passed to the phase lock loop circuits to extract the original

data and synchronous clock.

Data conversions of NRZI data to NRZ and serial-to-parallel: after data is recovered, the

signals are passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream.

This serial bit stream is packed to parallel 5B type for further processing. The NRZI to NRZ

conversion can be bypassed by clearing bit 7 of the RN13 register to 0.

De-scrambling and decoding of 5B/4B: The parallel 5B type data is passed to the

descrambler and 5B/4B decoder to extract the original MII nibble data.

Carrier sensing: the carrier sense (CRS) signal is asserted when the ST802RT1x detects

any 2 non-contiguous zeros within any 10-bit boundary of the receiving bit stream. CRS is

de-asserted when an ESD code-group or idle code-group is detected. In half-duplex mode,

CRS is asserted during packet transmission or receive. In full-duplex mode, CRS is

asserted only during packet reception.

RMII mode: this uses a reference clock (SCLK) of 50 MHz. 5B code groups are converted to

4-bit nibbles and the data is sent through a FIFO to the RMII receive data pins as dibits. In

case of an invalid code group in the data stream, the RXER signal is asserted and the 4 bits

of the receive data pins are driven with a specific code signalling the type of error detected.

For RMII mode, the CRS and RXDV pins combine their functionality into the RXDV pin (pin

38). The RXDV pin toggles at the end of a frame to indicate that the data is being emptied

from the internal FIFOs.

ST802RT1AFR 数据表(PDF) 39 Page - STMicroelectronics

ST802RT1AFR 数据表(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载