ST802RT1AFR datasheet(41/58 Pages) STMICROELECTRONICS

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ST802RT1A, ST802RT1B

Device operation

Doc ID 17049 Rev 1

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Auto-negotiation exchanges information with the network partner using the fast link pulses

(FLPs) - a burst of link pulses. FLP’s contain 16 bits of signaling information to advertise all

supported capabilities, determined by register RN04 (auto-negotiation advertisement

common capability by following the priority sequence below:

1. 100Base-TX full-duplex (highest priority)

2. 100Base-TX half-duplex

3. 10Base-T full-duplex

4. 10Base-T half-duplex (lowest priority)

During power-up or reset, if auto-negotiation is found enabled, then FLPs is transmitted and

the auto-negotiation function proceeds. Otherwise, the auto-negotiation does not occur until

the bit 12 of RN00 register is set to 1. When auto-negotiation is disabled, then the Network

Speed and Duplex Mode are selected by programming RN00 register.

7.8

Power-down / interrupt

The power-down and interrupt functions are multiplexed on pin 9 of the device. By default,

this pin functions as a power-down input and the interrupt function is disabled. Setting bit 8

(INT_OE_N) of RN12 (0x12h) configures the pin as active low interrupt output.

7.9

Power-down operation

To reduce power consumption, the ST802RT1x is designed with a power-down feature,

which can reduce power consumption significantly. Since the power supply of the 100Base-

TX and 10Base-T circuits are separated, the ST802RT1x can turn off the circuit of either the

100Base-TX or 10Base-T when the other one is operating. There is also a power-down

mode which can be selected by bit 11 in register RN00. During power-down mode, the

TXP/TXN outputs and all LED outputs are 3-stated, and the MII interface is isolated. During

power-down mode the MII management interface is still available for reading and writing

device registers. Power-down mode can be exited by clearing bit 11 of register RN00, or by

a hardware or software reset (setting RN00[15]=1). An external control signal can be used

to drive the pin PWRDWN/MDINT low, overcoming the weak internal pull-up resistor.

Alternatively, the device can be configured to initialize into a power-down state by placing an

external pull-down resistor on the PWRDWN/MDINT pin. Since the device still responds to

management register access, setting the INT_OE_N in the RN12 register disables the

PWRDWN/MDINT input, allowing the device to exit the power-down state.

7.10

Interrupt mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by

default. Setting bit 7 (INT_EN) of RN12 (0x12h) enables interrupts to be output, based on

the interrupt mask set in the lower byte of RN12 (0x12h). The PWRDWN/MDINT pin is

asynchronously asserted low when an interrupt condition occurs. The source of the interrupt

can be determined by reading the lower byte of RN11 (0x11h). One or more bits in the RN11

is set, denoting all currently pending interrupts.

Example: To generate an interrupt on a change of link status, the steps would be:

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