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PIC24FJ64GA 数据表(PDF) 28 Page - Microchip Technology |
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PIC24FJ64GA 数据表(HTML) 28 Page - Microchip Technology |
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28 / 52 page  PIC24FJXXXGA0XX DS39768D-page 28 © 2008 Microchip Technology Inc. FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE 4.3 Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. The MCLR pin is briefly driven high, then low. 2. A 32-bit key sequence is clocked into PGDx. 3. MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA0XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexa- decimal format). The device will enter Program/Verify mode only if the key sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE Is Start Enter ICSP™ Mode Application ID BBh? Resident in Memory Yes No Prog. Executive is Application ID Read the be Programmed Prog. Executive must from Address 807F0h Finish MCLR PGDx PGCx VDD P6 P14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... Program/Verify Entry Code = 4D434850h P1A P1B P18 P19 01 00 1 0 0 0 0 P7 VIH VIH |
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