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PIC24FJ64GA 数据表(PDF) 12 Page - Microchip Technology |
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PIC24FJ64GA 数据表(HTML) 12 Page - Microchip Technology |
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12 / 52 page  PIC24FJXXXGA0XX DS39768D-page 12 © 2008 Microchip Technology Inc. 3.0 DEVICE PROGRAMMING – ICSP ICSP mode is a special programming protocol that allows you to read and write to PIC24FJXXXGA0XX device family memory. The ICSP mode is the most direct method used to program the device; note, how- ever, that Enhanced ICSP is faster. ICSP mode also has the ability to read the contents of executive memory to determine if the programming executive is present. This capability is accomplished by applying control codes and instructions, serially to the device, using pins, PGCx and PGDx. In ICSP mode, the system clock is taken from the PGCx pin, regardless of the device’s oscillator Config- uration bits. All instructions are shifted serially into an internal buffer, then loaded into the Instruction Register (IR) and executed. No program fetching occurs from internal memory. Instructions are fed in 24 bits at a time. PGDx is used to shift data in and PGCx is used as both the serial shift clock and the CPU execution clock. 3.1 Overview of the Programming Process Figure 3-1 shows the high-level overview of the programming process. After entering ICSP mode, the first action is to Chip Erase the device. Next, the code memory is programmed, followed by the device Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. Then, program the code-protect Configuration bits, if required. FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW 3.2 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. Execution of the CPU is governed by an internal state machine. A 4-bit control code is clocked in using PGCx and PGDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution, and the REGOUT control code is used to read data out of the device via the VISI register. TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE Note: During ICSP operation, the operating frequency of PGCx must not exceed 10 MHz. 4-Bit Control Code Mnemonic Description 0000b SIX Shift in 24-bit instruction and execute. 0001b REGOUT Shift out the VISI (0784h) register. 0010b-1111b N/A Reserved. Start Perform Chip Erase Program Memory Verify Program Done Enter ICSP™ Program Configuration Bits Verify Configuration Bits Exit ICSP |
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